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| ? 2013 microchip technology inc. ds20005207a-page 1 MCP41HVX1 features ? high-voltage analog support: - +36v terminal voltage range (dgnd = v-) - 18v terminal voltage range (dgnd = v- + 18v) ? wide operating voltage: - analog: 10v to 36v (specified performance) - digital: 2.7v to 5.5v 1.8v to 5.5v (dgnd ? v- + 0.9v) ? single resistor network ? potentiometer configuration options ? resistor network resolution - 7-bit: 127 resistors (128 taps) - 8-bit: 255 resistors (256 taps) ?r ab resistance options: -5k ??? 10 k ? -50k ??? 100 k ? ? high terminal/wiper current (i w ) support: - 25ma (for 5k ? ) - 12.5 ma (for 10 k ? ) - 6.5 ma (for 50 k ? and 100 k ? ) ? zero-scale to full-scale wiper operation ? low wiper resistance: 75 ? (typical) ?low tempco: - absolute (rheostat): 50 ppm typical (0c to +70c) - ratiometric (potentiometer): 15 ppm typical ? spi serial interface (10 mhz, modes 0,0 and 1,1 ) ? resistor network terminal disconnect via: - shutdown pin (shdn ) - terminal control (tcon) register ? write latch (wlat ) pin to control update of volatile wiper register (such as zero crossing) ? power-on reset / brown-out reset for both: - digital supply (v l /dgnd); 1.5v typical - analog supply (v+ / v-); 3.5v typical ? serial interface inactive current (3 a typical) ? 500 khz typical bandwidth (-3 db) operation (5.0 k ? device) ? extended temperature range (-40c to +125c) ? package types: tssop-14 and qfn-20 (5x5) package types (top view) description the MCP41HVX1 family of devices have dual power rails (analog and digital). the analog power rail allows high voltage on the resistor network terminal pins. the analog voltage range is determined by the v+ and v? voltages. the maximum analog voltage is +36v, while the operating analog output minimum specifications are specified from either 10v or 20v. as the analog supply voltage becomes smaller, the analog switch resistances increase, which effect certain performance specifications. the system can be implemented as dual rail (18v) relative to the digital logic ground (dgnd). the device also has a write latch (wlat ) function, which will inhibit the volatile wiper register from being updated (latched) with the received data, until the wlat pin is low. this allows the application to specify a condition where the volatile wiper register is updated (such as zero crossing). MCP41HVX1 single potentiometer 1 2 3 4 11 12 13 14 v- p0b dgnd p0w 5 6 7 8 9 10 v+ nc ( 2 ) p0a sck v l shdn wlat cs sdo sdi 1 2 3 4 14 15 17 18 nc ( 2 ) nc ( 2 ) 6 7 89 12 13 p0b p0w v- nc ( 2 ) nc ( 2 ) shdn sdi v l cs sck 19 20 wlat nc ( 2 ) nc ( 2 ) p0a 5 sdo 10 nc ( 2 ) 11 dgnd 16 v+ 21 ep ( 1 ) note 1: exposed pad (ep) 2: nc = not internally connected tssop (st) 5x5 qfn (mq) 7/8-bit single, +36v (18v) digital pot with spi serial interf ace and volatile memory
MCP41HVX1 ds20005207a-page 2 ? 2013 microchip technology inc. device block diagram device features device # of pots wiper configuration control interface por wiper setting resistance (typical) number of: specified operating range r ab options (k ? ) wiper - r w ( ? ) r s taps v l ( 2 ) v+ ( 3 ) mcp41hv31 1 potentiometer ( 1 ) spi 3fh 5.0, 10.0, 50.0, 100.0 75 127 128 1.8v to 5.5v 10v ( 4 ) to 36v mcp41hv51 1 potentiometer ( 1 ) spi 7fh 5.0, 10.0, 50.0, 100.0 75 255 256 1.8v to 5.5v 10v ( 4 ) to 36v note 1: floating either terminal (a or b) allows the device to be used as a rheostat (variable resistor). 2: this is relative to the dgnd signal. there is a separate requirement for the v+ / v- voltages. when v l = 1.8v operation, dgnd must be 0.9v above v-. 3: relative to v-, the v l and dgnd signals must be between v- and v+. 4: analog operation will continue while the v+ voltage is above the device?s analog power-on reset (por) / brown-out reset (bor) voltage. operational characteristics may exceed specified limits while the v+ volt- age is below the specified minimum voltage. power-up/ brown-out control v l dgnd spi serial interface module and control logic resistor network 0 (pot 0) wiper 0 and tcon register cs sck sdi sdo shdn memory (2x8) wiper0 (v) tcon p0a p0w p0b v+ v? wlat power-up/ brown-out control (analog) (digital) ? 2013 microchip technology inc. ds20005207a-page 3 MCP41HVX1 1.0 electrical characteristics absolute maximum ratings ? voltage on v- with respect to dgnd ......................................................................................... dg nd + 0.6v to -40.0v voltage on v+ with respect to dgnd ........................................................................................... dgnd - 0.3v to 40.0v voltage on v+ with respect to v- .............................................................................................. .... dgnd - 0.3v to 40.0v voltage on v l with respect to v+ ........................................................................................................... . -0.6v to -40.0v voltage on v l with respect to v- ........................................................................................................... .. -0.6v to +40.0v voltage on v l with respect to dgnd ....................................................................................................... - 0.6v to +7.0v voltage on cs , sck, sdi, wlat , and shdn with respect to dgnd ................................................ -0.6v to v l + 0.6v voltage on all other pins (pxa, pxw, and pxb) with respect to v- ......................................................-0.3v to v+ + 0.3v input clamp current, i ik (v i < 0, v i > v l , v i > v pp on hv pins) ............................................................................ 20 ma output clamp current, i ok (v o < 0 or v o > v l ) ................................................................................................... 20 ma maximum current out of dgnd pin ................................................................................................ ...................... 100 ma maximum current into v l pin........................................................................................................................... ..... 100 ma maximum current out of v- pin .................................................................................................. ........................... 100 ma maximum current into v+ pin .................................................................................................... ............................100 ma maximum current into p x a, p x w, & p x b pins (continuous) r ab = 5 k ? ............................................................................................................................. 25 ma r ab = 10 k ? ........................................................................................................................ 12.5 ma r ab = 50 k ? .......................................................................................................................... 6. 5ma r ab = 100 k ? ........................................................................................................................ 6.5 m a maximum current into p x a, p x w, & p x b pins (pulsed) f pulse > 10 khz ......................................................................................................... (max i continuous ) / (duty cycle) f pulse ? 10 khz ...................................................................................................... (max i continuous ) / ?? (duty cycle) maximum output current sunk by any output pin ................................................................................. ................. 25 ma maximum output current sourced by any output pin .............................................................................. .............. 25 ma package power dissipation (t a = + 50c, t j = +150c) tssop-14 ...................................................................................................................... ....................... 1000 mw soic-16 ....................................................................................................................... ......................... 1250 mw qfn-20 (5 x 5) ................................................................................................................ ...................... 2800 mw qfn-20 (4x4) ................................................................................................................... ...................... 2300 mw soldering temperature of leads (10 seconds) ................................................................................... .................. +300c esd protection on all pins human body model (hbm) ........................................................................................................ .............. ? 4 kv machine model (mm) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????? ??????????????? ??? 400v maximum junction temperature (t j ) ..................................................................................................................... 150c storage temperature ........................................................................................................... .................. -65c to +150c ambient temperature with power applied ........................................................................................ ...... -40c to +125c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. MCP41HVX1 ds20005207a-page 4 ? 2013 microchip technology inc. ac/dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions digital positive supply voltage (v l ) v l 2.7 ? 5.5 v with respect to dgnd ( note 4 ) 1.8 ? 5.5 v dgnd = v- + 0.9v (referenced to v-) ( note 1 , note 4 ) ? ? 0 v with respect to v+ analog positive supply voltage (v+) v+ v l ( 16 ) ? 36.0 v with respect to v- ( note 4 ) digital ground voltage (dgnd) v dgnd v- ? v+ - v l v with respect to v- ( note 4 , note 5 ) analog negative supply voltage (v-) v- -36.0 + v l ? 0 v with respect to dgnd and v l = 1.8v resistor network supply voltage v rn ? ? 36v v delta voltage between v+ and v- ( note 4 ) v l start voltage to ensure wiper reset v dpor ? ? 1.8 v with respect to dgnd, v+ > 6.0v ram retention voltage (v ram ) < v dbor v+ voltage to ensure wiper reset v apor ? ? 6.0 v with respect to v-, v l = 0v ram retention voltage (v ram ) < v bor digital to analog level shifter operational voltage v ls ??2.3 vv l to v- voltage. dgnd = v- power rail voltages during power up ( note 1 ) v lpor ? ? 5.5 v digital powers (v l / dgnd) up 1st: v+ and v- floating or as v+ / v- powers up (v+ must be ? to dgnd) ( note 18 ) v+ por ? ? 36 v analog powers (v+ / v-) up 1st: v l and dgnd floating or as v l / dgnd powers up (dgnd must be between v- and v+) ( note 18 ) v l rise rate to ensure power-on reset v lrr ( note 6 ) v/ms with respect to dgnd note 1 this specification by design. note 4 v+ voltage is dependent on v- voltage. the maximum delta voltage between v+ and v- is 36v. the digital logic dgnd potential can be anywhere between v+ and v-, the v l potential must be ?? dgnd and ?? v+. note 5 minimum value determined by maximum v- to v+ potential equals 36v and minimum v l = 1.8v for opera- tion. so 36v - 1.8v = 34.2v. note 6 por/bor is not rate dependent. note 16 for specified analog performance, v+ must be 20v or greater (unless otherwise noted). note 18 during the power up sequence, to ensure expected analog por operation, the two power systems (analog and digital) should have a common reference to ensure that the driven dgnd voltage is not at a higher potential than the driven v+ voltage. ? 2013 microchip technology inc. ds20005207a-page 5 MCP41HVX1 ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions delay after device exits the reset state (v l > v bor ) t bord ?10 20s supply current ? ( note 7 ) i ddd ? 45 300 a serial interface active, write all 0 ?s to volatile wiper 0 (address 0h) v l = 5.5v, cs = v il , f sck = 5 mhz, v- = dgnd ? ? 7 a serial interface inactive, v l = 5.5v, sck = v ih , cs = v ih , wiper = 0, v- = dgnd i dda ? ? 5 a current v+ to v-, pxa = pxb = pxw, dgnd = v- +(v+/2) resistance ( 20%) ? ( note 8 ) r ab 4.0 5 6.0 k ? -502 devices, v+/v- = 10v to 36v 8.0 10 12.0 k ? -103 devices, v+/v- = 10v to 36v 40.0 50 60.0 k ? -503 devices, v+/v- = 10v to 36v 80.0 100 120.0 k ? -104 devices, v+/v- = 10v to 36v r ab current i ab ? ? 9.00 ma -502 devices 36v / r ab(min) , v- = -18v, v+ = +18v, ( note 9 ) ? ? 4.50 ma -103 devices ? ? 0.90 ma -503 devices ? ? 0.45 ma -104 devices resolution n 256 taps 8-bit no missing codes 128 taps 7-bit no missing codes step resistance (see appendix b.4 ) r s ?r ab / (255) ? ? 8-bit note 1 ?r ab / (127) ? ? 7-bit note 1 note 1 this specification by design. note 7 supply current (iddd and idda) is independent of current through the resistor network. note 8 resistance (rab) is defined as the resistance between terminal a to terminal b. note 9 guaranteed by the r ab specification and ohms law. MCP41HVX1 ds20005207a-page 6 ? 2013 microchip technology inc. ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions wiper resistance (see appendix b.5 ) r w ? 75 170 ? i w = 1 ma v+ = +18v, v- = -18v, code = 00h, pxa = floating, pxb = v-. ? 145 200 ? i w = 1 ma v+ = +5.0v, v- = -5.0v, code = 00h, pxa = floating, pxb = v-. ( note 2 ) nominal resistance te m p c o (see appendix b.23 ) ? r ab / ? t ?50 ?ppm/ct a = -40c to +85c ? 100 ? ppm/c t a = -40c to +125c ratiometeric tempco (see appendix b.22 ) ? v wb / ? t ? 15 ? ppm/c code = mid-scale (80h or 40h) resistor terminal input voltage range (terminals a, b and w) v a, v w, v b v- ? v+ v note 1 , note 11 current through te r m i n a l s (a, b, and wiper) ( note 1 ) i t , i w ? ? 25 ma -502 devices i bw( w zs ) and i aw( w fs ) ? ? 12.5 ma -103 devices i bw( w zs ) and i aw( w fs ) ? ? 6.5 ma -503 devices i bw( w zs ) and i aw( w fs ) ? ? 6.5 ma -104 devices i bw( w zs ) and i aw( w fs ) ??36 mai bw( w = zs ) , or i aw( w = fs ) leakage current into a, w or b i tl ? 5 ? na a = w = b = v- note 1 this specification by design. note 2 this parameter is not tested, but specified by characterization. note 11 resistor terminals a, w and b?s polarity with respect to each other is not restricted. ? 2013 microchip technology inc. ds20005207a-page 7 MCP41HVX1 ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions full scale error (potentiometer) (8-bit code = ffh, 7-bit code = 7fh) ( note 10 , note 17 ) ( v a = v+, v b = v- ) (see appendix b.10 ) v wfse -8.5 ? ? lsb 5 k ? 8-bit v ab = 20v to 36v -13.5 ? ? lsb v ab = 10v to 36v -4.5 ? ? lsb 7-bit v ab = 20v to 36v -7.0 ? ? lsb v ab = 10v to 36v -4.5 ? ? lsb 10 k ? 8-bit v ab = 20v to 36v -6.0 ? ? lsb v ab = 10v to 36v -2.25 ? ? lsb 7-bit v ab = 20v to 36v -3.5 ? ? lsb v ab = 10v to 36v -0.9 ? ? lsb 50 k ? 8-bit v ab = 20v to 36v -1.25 ? ? lsb v ab = 10v to 36v -0.95 ? ? lsb 7-bit v ab = 20v to 36v -1.1 ? ? lsb v ab = 10v to 36v -0.5 ? ? lsb 100 k ? 8-bit v ab = 20v to 36v -0.7 ? ? lsb v ab = 10v to 36v -0.75 ? ? lsb 7-bit v ab = 20v to 36v -0.9 ? ? lsb v ab = 10v to 36v zero scale error (potentiometer) (8-bit code = 00h, 7-bit code = 00h) ( note 10 , note 17 ) ( v a = v+, v b = v- ) (see appendix b.11 ) v wzse ??+8.5lsb5k ? 8-bit v ab = 20v to 36v ? ? +13.5 lsb v ab = 10v to 36v ??+4.5lsb 7-bit v ab = 20v to 36v ? ? +7.0 lsb v ab = 10v to 36v ??+4.0lsb10k ? 8-bit v ab = 20v to 36v ? ? +6.0 lsb v ab = 10v to 36v ??+2.0lsb 7-bit v ab = 20v to 36v ? ? +3.0 lsb v ab = 10v to 36v ??+0.8lsb50k ? 8-bit v ab = 20v to 36v ? ? +1.2 lsb v ab = 10v to 36v ??+0.5lsb 7-bit v ab = 20v to 36v ? ? +0.7 lsb v ab = 10v to 36v ? ? +0.5 lsb 100 k ? 8-bit v ab = 20v to 36v ? ? +0.7 lsb v ab = 10v to 36v ??+0.25lsb 7-bit v ab = 20v to 36v ? ? +0.4 lsb v ab = 10v to 36v note 10 measured at v w with v a = v+ and v b = v- . note 17 analog switch leakage effects this specification. higher temperatures increase the switch leakage. MCP41HVX1 ds20005207a-page 8 ? 2013 microchip technology inc. ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions potentiometer integral non-linearity ( note 10 , note 17 ) (see appendix b.12 ) p-inl -1 0.5 +1 lsb 5 k ? 8-bit v ab = 10v to 36v -0.5 0.25 +0.5 lsb 7-bit v ab = 10v to 36v -1 0.5 +1 lsb 10 k ? 8-bit v ab = 10v to 36v -0.5 0.25 +0.5 lsb 7-bit v ab = 10v to 36v -1.1 0.5 +1.1 lsb 50 k ? 8-bit v ab = 10v to 36v -1 0.5 +1 lsb v ab = 20v to 36v, ( note 2 ) -1 0.5 +1 lsb v ab = 10v to 36v, ?40c ? t a ? +85c ( note 2 ) -0.6 0.25 +0.6 lsb 7-bit v ab = 10v to 36v -1.85 0.5 +1.85 lsb 100 k ? 8-bit v ab = 10v to 36v -1.2 0.5 +1.2 lsb v ab = 20v to 36v, ( note 2 ) -1 0.5 +1 lsb v ab = 10v to 36v, ?40c ? t a ? +85c ( note 2 ) -1 0.5 +1 lsb 7-bit v ab = 10v to 36v potentiometer differential non-linearity ( note 10 , note 17 ) (see appendix b.13 ) p-dnl -0.5 0.25 +0.5 lsb 5 k ? 8-bit v ab = 10v to 36v -0.25 0.125 +0.25 lsb 7-bit v ab = 10v to 36v -0.25 0.125 +0.25 lsb 10 k ? 8-bit v ab = 10v to 36v -0.125 0.1 +0.125 lsb 7-bit v ab = 10v to 36v -0.25 0.125 +0.25 lsb 50 k ? 8-bit v ab = 10v to 36v -0.125 0.1 +0.125 lsb 7-bit v ab = 10v to 36v -0.25 0.125 +0.25 lsb 100 k ? 8-bit v ab = 10v to 36v -0.125 -0.15 +0.125 lsb 7-bit v ab = 10v to 36v note 2 this parameter is not tested, but specified by characterization. note 10 measured at v w with v a = v+ and v b = v- . note 17 analog switch leakage effects this specification. higher temperatures increase the switch leakage. ? 2013 microchip technology inc. ds20005207a-page 9 MCP41HVX1 ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions bandwidth -3 db (load = 30 pf) bw ? 480 ? khz 5 k ? 8-bit code = 7fh ? 480 ? khz 7-bit code = 3fh ?240 ? khz10k ? 8-bit code = 7fh ? 240 ? khz 7-bit code = 3fh ?48 ? khz50k ? 8-bit code = 7fh ? 48 ? khz 7-bit code = 3fh ?24 ? khz100k ? 8-bit code = 7fh ? 24 ? khz 7-bit code = 3fh v w settling time (v a = 10v, v b = 0v, 1lsb error band, c l = 50 pf ) (see appendix b.17 ) t s ?1 ? s5k ? code = 00h -> ffh (7fh); ffh (7fh) -> 00h ?1 ? s10k ? code = 00h -> ffh (7fh); ffh (7fh) -> 00h ?2.5 ? s50k ? code = 00h -> ffh (7fh); ffh (7fh) -> 00h ?5 ? s100k ? code = 00h -> ffh (7fh); ffh (7fh) -> 00h MCP41HVX1 ds20005207a-page 10 ? 2013 microchip technology inc. ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions rheostat integral non-linearity ( note 12 , note 13 , note 14 , note 17 ) (see appendix b.5 ) r-inl -1.75 ? +1.75 lsb 5 k ? 8-bit i w = 6.0 ma, (v+ - v-) = 36v ( note 2 ) -2.5 ? +2.5 lsb i w = 3.3 ma, (v+ - v-) = 20v ( note 2 ) -4.0 ? +4.0 lsb i w = 1.7 ma, (v+ - v-) = 10v -1.0 ? +1.0 lsb 7-bit i w = 6.0 ma, (v+ - v-) = 36v ( note 2 ) -1.5 ? +1.5 lsb i w = 3.3 ma, (v+ - v-) = 20v ( note 2 ) -2.0 ? +2.0 lsb i w = 1.7 ma, (v+ - v-) = 10v -1.0 ? +1.0 lsb 10 k ? 8-bit i w = 3.0 ma, (v+ - v-) = 36v ( note 2 ) -1.75 ? +1.75 lsb i w = 1.7 ma, (v+ - v-) = 20v ( note 2 ) -2.0 ? +2.0 lsb i w = 830 a, (v+ - v-) = 10v -0.5 ? +0.5 lsb 7-bit i w = 3.0 ma, (v+ - v-) = 36v ( note 2 ) -0.8 ? +0.8 lsb i w = 1.7 ma, (v+ - v-) = 20v ( note 2 ) -1.0 ? +1.0 lsb i w = 830 a, (v+ - v-) = 10v -1.0 ? +1.0 lsb 50 k ? 8-bit i w = 600 a, (v+ - v-) = 36v ( note 2 ) -1.0 ? +1.0 lsb i w = 330 a, (v+ - v-) = 20v ( note 2 ) -1.2 ? +1.2 lsb i w = 170 a, (v+ - v-) = 10v -0.5 ? +0.5 lsb 7-bit i w = 600 a, (v+ - v-) = 36v ( note 2 ) -0.5 ? +0.5 lsb i w = 330 a, (v+ - v-) = 20v ( note 2 ) -0.6 ? +0.6 lsb i w = 170 a, (v+ - v-) = 10v -1.0 ? +1.0 lsb 100 k ? 8-bit i w = 300 a, (v+ - v-) = 36v ( note 2 ) -1.0 ? +1.0 lsb i w = 170 a, (v+ - v-) = 20v ( note 2 ) -1.2 ? +1.2 lsb i w = 83 a, (v+ - v-) = 10v -0.5 ? +0.5 lsb 7-bit i w = 300 a, (v+ - v-) = 36v ( note 2 ) -0.5 ? +0.5 lsb i w = 170 a, (v+ - v-) = 20v ( note 2 ) -0.6 ? +0.6 lsb i w = 83 a, (v+ - v-) = 10v note 2 this parameter is not tested, but specified by characterization. note 12 non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. note 13 externally connected to a rheostat configuration (rbw), and then tested. note 14 wiper current (i w ) condition determined by r ab(max) and voltage condition, the delta voltage between v+ and v- (voltages are 36v, 20v, and 10v). note 17 analog switch leakage effects this specification. higher temperatures increase the switch leakage. ? 2013 microchip technology inc. ds20005207a-page 11 MCP41HVX1 ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions rheostat differential non-linearity ( note 12 , note 13 , note 14 , note 17 ) (see appendix b.5 ) r-dnl -0.5 ? +0.5 lsb 5 k ? 8-bit i w = 6.0 ma, (v+ - v-) = 36v ( note 2 ) -0.5 ? +0.5 lsb i w = 3.3 ma, (v+ - v-) = 20v ( note 2 ) -0.6 ? +0.6 lsb i w = 1.7 ma, (v+ - v-) = 10v -0.25 ? +0.25 lsb 7-bit i w = 6.0 ma, (v+ - v-) = 36v ( note 2 ) -0.25 ? +0.25 lsb i w = 3.3 ma, (v+ - v-) = 20v ( note 2 ) -0.3 ? +0.3 lsb i w = 1.7 ma, (v+ - v-) = 10v -0.5 ? +0.5 lsb 10 k ? 8-bit i w = 3.0 ma, (v+ - v-) = 36v ( note 2 ) -0.5 ? +0.5 lsb i w = 1.7 ma, (v+ - v-) = 20v ( note 2 ) -0.5 ? +0.5 lsb i w = 830 a, (v+ - v-) = 10v -0.25 ? +0.25 lsb 7-bit i w = 3.0 ma, (v+ - v-) = 36v ( note 2 ) -0.25 ? +0.25 lsb i w = 1.7 ma, (v+ - v-) = 20v ( note 2 ) -0.25 ? +0.25 lsb i w = 830 a, (v+ - v-) = 10v -0.5 ? +0.5 lsb 50 k ? 8-bit i w = 600 a, (v+ - v-) = 36v ( note 2 ) -0.5 ? +0.5 lsb i w = 330 a, (v+ - v-) = 20v ( note 2 ) -0.5 ? +0.5 lsb i w = 170 a, (v+ - v-) = 10v -0.25 ? +0.25 lsb 7-bit i w = 600 a, (v+ - v-) = 36v ( note 2 ) -0.25 ? +0.25 lsb i w = 330 a, (v+ - v-) = 20v ( note 2 ) -0.25 ? +0.25 lsb i w = 170 a, (v+ - v-) = 10v -0.5 ? +0.5 lsb 100 k ? 8-bit i w = 300 a, (v+ - v-) = 36v ( note 2 ) -0.5 ? +0.5 lsb i w = 170 a, (v+ - v-) = 20v ( note 2 ) -0.5 ? +0.5 lsb i w = 83 a, (v+ - v-) = 10v -0.25 ? +0.25 lsb 7-bit i w = 300 a, (v+ - v-) = 36v ( note 2 ) -0.25 ? +0.25 lsb i w = 170 a, (v+ - v-) = 20v ( note 2 ) -0.25 ? +0.25 lsb i w = 83 a, (v+ - v-) = 10v note 2 this parameter is not tested, but specified by characterization. note 12 non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. note 13 externally connected to a rheostat configuration (rbw), and then tested. note 14 wiper current (i w ) condition determined by r ab(max) and voltage condition, the delta voltage between v+ and v- (voltages are 36v, 20v, and 10v). note 17 analog switch leakage effects this specification. higher temperatures increase the switch leakage. MCP41HVX1 ds20005207a-page 12 ? 2013 microchip technology inc. ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions capacitance (p a )c a ? 75 ? pf measured to v-, f =1 mhz, wiper code = mid-scale capacitance (p w )c w ? 120 ? pf measured to v-, f =1 mhz, wiper code = mid-scale capacitance (p b )c b ? 75 ? pf measured to v-, f =1 mhz, wiper code = mid-scale common-mode leakage i cm ?5?nav a = v b = v w digital interface pin capacitance c in , c out ?10?pff c = 400 khz digital inputs/outputs (cs , sdi, sdo, sck, shdn , wlat ) schmitt trigger high- input threshold v ih 0.45 v l ?v l + 0.3v v 2.7v ? v l ? 5.5v 0.5 v l ?v l + 0.3v v 1.8v ? v l ? 2.7v schmitt trigger low- input threshold v il dgnd - 0.5v ? 0.2 v l v hysteresis of schmitt trigger inputs v hys ?0.1v l ?v output low voltage (sdo) v ol dgnd ? 0.2 v l vv l = 5.5v, i ol = 5 ma dgnd ? 0.2 v l vv l = 1.8v, i ol = 800 ua output high voltage (sdo) v oh 0.8 v l ?v l vv l = 5.5v, i oh = -2.5 ma 0.8 v l ?v l vv l = 1.8v, i ol = -800 ua input leakage current i il -1 1 ua v in = v l and v in = dgnd ? 2013 microchip technology inc. ds20005207a-page 13 MCP41HVX1 ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -1 8v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions ram (wiper, tcon) value wiper value range n 0h ? ffh hex 8-bit 0h ? 7fh hex 7-bit wiper por/bor value n por/bor 7fh hex 8-bit 3fh hex 7-bit tcon value range n 0h ? ffh hex tcon por/bor value n tcon ff hex all terminals connected power requirements power supply sensitivity (see appendix b.20 ) pss ? 0.0015 0.0035 %/% 8-bit v l = 2.7v to 5.5v, v+ = 18v, v- = -18v, code = 7fh ? 0.0015 0.0035 %/% 7-bit v l = 2.7v to 5.5v, v+ = 18v, v- = -18v, code = 3fh power dissipation p diss ?260 ?mw5k ? v l = 5.5v, v+ = 18v, v- = -18v ( note 15 ) ?130 ?mw10k ? ?26 ?mw50k ? ?13 ?mw100k ? note 15 p diss = i * v, or ( (i ddd * 5.5v) + (i dda * 36v) + (i ab * 36v) ). MCP41HVX1 ds20005207a-page 14 ? 2013 microchip technology inc. ac / dc notes: 1. this specification by design. 2. this parameter is not tested, but specified by characterization. 3. see absolute maximum ratings. 4. v+ voltage is dependent on v- voltage. the maximum delta voltage between v+ and v- is 36v. the digital logic dgnd potential can be anywhere between v+ and v-, the v l potential must be ?? dgnd and ?? v+. 5. minimum value determined by maximum v- to v+ potential equals 36v and minimum v l = 1.8v for operation. so 36v - 1.8v = 34.2v. 6. por/bor is not rate dependent. 7. supply current (i ddd and i dda ) is independent of current through the resistor network. 8. resistance (r ab ) is defined as the resistance between terminal a to terminal b. 9. guaranteed by the r ab specification and ohms law. 10. measured at v w with v a = v+ and v b = v-. 11. resistor terminals a, w and b?s polarity with respect to each other is not restricted. 12. non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 13. externally connected to a rheostat configuration (r bw ), and then tested. 14. wiper current (i w ) condition determined by r ab(max) and voltage condition, the delta voltage between v+ and v- (voltages are 36v, 20v, and 10v). 15. p diss = i * v, or ( (i ddd * 5.5v) + (i dda * 36v) + (i ab * 36v) ). 16. for specified analog performance, v+ must be 20v or greater (unless otherwise noted). 17. analog switch leakage effects this specification. higher temperatures increase the switch leakage. 18. during the power up sequence, to ensure expected analog por operation, the two power systems (analog and digital) should have a common reference to ensure that the driven dgnd voltage is not at a higher potential than the driven v+ voltage. ? 2013 microchip technology inc. ds20005207a-page 15 MCP41HVX1 1.1 spi mode timing waveforms and requirements figure 1-1: settling time waveforms. table 1-1: wiper settling timing figure 1-2: spi timing waveform (mode = 11 ). timing characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v+ = 10v to 36v (referenced to v-); v+ = +5v to +18v & v- = -5.0v to -18v (referenced to dgnd -> 5v to 18v), v l = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v l = 5.5v, t a = +25c. parameters sym min typ max units conditions v w settling time (v a = 10v, v b = 0v, 1lsb error band, c l = 50 pf ) t s ?1?s5k ? code = 00h -> ffh (7fh); ffh (7fh) -> 00h ?1?s10k ? code = 00h -> ffh (7fh); ffh (7fh) -> 00h ?2.5?s50k ? code = 00h -> ffh (7fh); ffh (7fh) -> 00h ?5?s100k ? code = 00h -> ffh (7fh); ffh (7fh) -> 00h w 1 lsb old value new value cs sck sdo sdi 70a 72 71 73 74 77 80 msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 84 wlat ? 0 ? ? 0 ? ? 1 ? ? 1 ? 83b 70b 85 83a MCP41HVX1 ds20005207a-page 16 ? 2013 microchip technology inc. table 1-2: spi requirements (mode = 11 ) figure 1-3: spi timing waveform (mode = 00 ). # characteristic symbol min max units conditions sck input frequency f sck ?10mhzv l = 2.7v to 5.5v ?1mhzv l = 1.8v to 2.7v 70a cs active (v il ) to sck ? input tcsa2sch 25 ? ns 70b wlat active (v il ) to eighth (or sixteenth) sck ? of the serial command to ensure previous data is latched (setup time) twla2sch 20 ? ns 71 sck input high time tsch 35 ? ns v l = 2.7v to 5.5v 120 ? ns v l = 1.8v to 2.7v 72 sck input low time tscl 35 ? ns v l = 2.7v to 5.5v 120 ? ns v l = 1.8v to 2.7v 73 setup time of sdi input to sck ? edge t di v2sch 10 ? ns 74 hold time of sdi input from sck ? edge tsch2 di l20 ?ns 77 cs inactive (v ih ) to sdo output high-impedance tcsh2 do z? 50ns note 1 80 sdo data output valid after sck ? edge tscl2 do v? 55nsv l = 2.7v to 5.5v 90 ns v l = 1.8v to 2.7v 83a cs inactive (v ih ) after sck ? edge tsch2csi 100 ? ns 83b wlat inactive (v ih ) after eighth (or sixteenth) sck ? edge (hold time) tsch2wlati 50 ? ns 84 hold time of cs (or wlat ) inactive (v ih ) to cs (or wlat ) active (v il ) tcsa2csi 20 ? ns 85 wlat input low time t wlat l25?ns note 1: this specification by design. cs sck sdo sdi 70a 71 72 82 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83a 84 73 wlat ? 0 ? ? 0 ? ? 1 ? ? 1 ? 70b 83b ? 2013 microchip technology inc. ds20005207a-page 17 MCP41HVX1 table 1-3: spi requirements (mode = 00 ) # characteristic symbol min max units conditions sck input frequency f sck ?10mhzv l = 2.7v to 5.5v ?1mhzv l = 1.8v to 2.7v 70a cs active (v il ) to sck ? input tcsa2sch 25 ? ns 70b wlat active (v il ) to eighth (or sixteenth) sck ? of the serial command to ensure previous data is latched (setup time) twla2sch 20 ? ns 71 sck input high time tsch 35 ? ns v l = 2.7v to 5.5v 120 ? ns v l = 1.8v to 2.7v 72 sck input low time tscl 35 ? ns v l = 2.7v to 5.5v 120 ? ns v l = 1.8v to 2.7v 73 setup time of sdi input to sck ? edge t di v2sch 10 ? ns 74 hold time of sdi input from sck ? edge tsch2 di l20 ?ns 77 cs inactive (v ih ) to sdo output high-impedance tcsh2 do z? 50ns note 1 80 sdo data output valid after sck ? edge tscl2 do v? 55nsv l = 2.7v to 5.5v 90 ns v l = 1.8v to 2.7v 82 sdo data output valid after cs active (v il ) tssl2dov ? 70 ns 83a cs inactive (v ih ) after sck ? edge tscl2csi 100 ? ns 83b wlat inactive (v ih ) after sck ? edge tscl2wlati 50 ? ns 84 hold time of cs (or wlat ) inactive (v ih ) to cs (or wlat ) active (v il ) tc s a 2 c s i 2 0 ? n s 85 wlat input low time t wlat l25?ns note 1: this specification by design. MCP41HVX1 ds20005207a-page 18 ? 2013 microchip technology inc. temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 14l-tssop (st) ? ja ?100?c/w thermal resistance, 20l-qfn (mq) ? ja ?36.1?c/w ? 2013 microchip technology inc. ds20005207a-page 19 MCP41HVX1 2.0 typical performance curves note: the device performance curves are available in a separate document. this is done to keep the file size of this pdf document less than the 10mb file attachment limit of many mail servers. the MCP41HVX1 performance curves document is literature number ds20005209, and can be found on the microchip website. look at the MCP41HVX1 product page under documentation and software, in the data sheets category. MCP41HVX1 ds20005207a-page 20 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds20005207a-page 21 MCP41HVX1 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . additional descriptions of the device pins follows. table 3-1: pinout description for the MCP41HVX1 pin function tssop qfn symbol type buffer type 14l 20l 11 v l p ? positive digital power supply input 2 2 sck i st spi serial clock pin 33 cs i st chip select 4 4 sdi i st spi serial data in pin 5 5 sdo o ? spi serial data out 66 wlat i st wiper latch enable 0 = received spi shift register buffer (spibuf) value is transferred to wiper register. 1 = received spi data value is held in spi shift register buffer (spibuf). 77 shdn istshutdown 8 11 dgnd p ? ground 9 8, 9, 10, 17, 18, 19, 20 nc ? ? pin not internally connected to die. to reduce noise coupling, connect pin either to dgnd or v l . 10 12 v- p ? analog negative potential supply 11 13 p0b i/o a potentiometer 0 terminal b 12 14 p0w i/o a potentiometer 0 wiper te r m i n a l 13 15 p0a i/o a potentiometer 0 terminal a 14 16 v+ p ? analog positive potential supply ? 21 ep p ? exposed pad, connect to v- signal or not connected (floating). ( note 1 ) legend: a = analog st = schmitt trigger i = input o = output i/o = input/output p = power note 1: the qfn package has a contact on the bottom of the package. this contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device?s v- pin. MCP41HVX1 ds20005207a-page 22 ? 2013 microchip technology inc. 3.1 positive power supply input (v l ) the v l pin is the device?s positive power supply input. the input power supply is relative to dgnd and can range from 1.8v to 5.5v. a de-coupling capacitor on v l (to dgnd) is recommended to achieve maximum performance. while the device?s v l < v min (2.7v), the electrical performance of the device may not meet the data sheet specifications. 3.2 serial clock (sck) the sck pin is the serial interface's serial clock pin. this pin is connected to the host controllers sck pin. the MCP41HVX1 is an spi slave device, so its sck pin is an input only pin. 3.3 chip select (cs ) the cs pin is the serial interface?s chip select input. forcing the cs pin to v il enables the serial commands. 3.4 serial data in (sdi) the sdi pin is the serial interfaces serial data in pin. this pin is connected to the host controller?s sdo pin. 3.5 serial data out (sdo) the sdo pin is the serial interface?s serial data out pin. this pin is connected to the host controller?s sdi pin. this pin allows the host controller to read the digital potentiometer registers (wiper and tcon), or monitor the state of the command error bit. 3.6 wiper latch (wlat ) the wlat pin is used to hold off the transfer of the received wiper value (in the shift register) to the wiper register. this allows this transfer to be synchronized to an external event (such as zero crossing). 3.7 shutdown (shdn ) the shdn pin is used to force the resistor network terminals into the hardware shutdown state. 3.8 digital ground (dgnd) the dgnd pin is the device?s digital ground reference. 3.9 not connected (nc) this pin is not internally connected to the die. to reduce noise coupling, these pins should be connected to either v l or dgnd. 3.10 analog negative voltage (v-) analog circuitry negative supply voltage. must not have a higher potential then the dgnd pin. 3.11 potentiometer terminal b the terminal b pin is connected to the internal potentiometer?s terminal b. the potentiometer?s terminal b is the fixed connection to the zero scale wiper value of the digital potentiometer. this corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. the terminal b pin does not have a polarity relative to the terminal w or a pins. the terminal b pin can support both positive and negative current. the voltage on terminal b must be between v+ and v-. 3.12 potentiometer wiper (w) terminal the terminal w pin is connected to the internal potentiometer?s terminal w (the wiper). the wiper terminal is the adjustable terminal of the digital potentiometer. the terminal w pin does not have a polarity relative to terminal?s a or b pins. the terminal w pin can support both positive and negative current. the voltage on terminal w must be between v+ and v-. if the v+ voltage powers up before the v l voltage, the wiper is forced to midscale once the analog por voltage is crossed. if the v+ voltage powers up after the v l voltage is greater than the digital por voltage, the wiper is forced to the value in the wiper register once the analog por voltage is crossed. 3.13 potentiometer terminal a the terminal a pin is connected to the internal potentiometer?s terminal a. the potentiometer?s terminal a is the fixed connection to the full scale wiper value of the digital potentiometer. this corresponds to a wiper value of 0xff for 8-bit devices or 0x7f for 7-bit devices. the terminal a pin does not have a polarity relative to the terminal w or b pins. the terminal a pin can support both positive and negative current. the voltage on terminal a must be between v+ and v-. 3.14 analog positive voltage (v+) analog circuitry positive supply voltage. must have a higher potential then the v- pin. 3.15 exposed pad (ep) this pad is only on the bottom of the qfn packages. this pad is conductively connect to the device substrate. the ep pin must be connected to the v- signal or left floating. this pad could be connected to a pcb heat sink to assist as a heat sink for the device. ? 2013 microchip technology inc. ds20005207a-page 23 MCP41HVX1 4.0 functional overview this data sheet covers a family of two volatile digital potentiometer devices that will be referred to as MCP41HVX1. as the device block diagram shows, there are six main functional blocks. these are: ? operating voltage range ? por/bor operation ? memory map ? control module ? resistor network ? serial interface (spi) the por/bor operation and the memory map are discussed in this section and the resistor network and spi operation are described in their own sections. the device commands are discussed in section 7.0 . 4.1 operating voltage range the MCP41HVX1 devices have four voltage signals. these are: ? v+ - analog power ?v l - digital power ? dgnd - digital ground ? v- - analog ground figure 4-1 shows the two possible power-up sequences; analog power rails power-up first, or digital power rails power-up first. the device has been designed so that either power rail may power-up first. the device has a por circuit for both digital power circuitry and analog power circuitry. if the v+ voltage powers-up before the v l voltage, the wiper is forced to midscale once the analog por voltage is crossed. if the v+ voltage powers-up after the v l voltage is greater than the digital por voltage, the wiper is forced to the value in the wiper register, once the analog por voltage is crossed. figure 4-2 shows the three cases of the digital power signals (v l / dgnd) with respect to the analog power signals (v+ / v-). the device implement level shifts between the digital and analog power systems, which allows the digital interface voltage to be anywhere in the v+ / v- voltage window. figure 4-1: power-on sequences. v- v+ dgnd v l v- v+ dgnd v l referenced to v- referenced to dgnd v- v+ dgnd v l v- v+ dgnd v l referenced to v- referenced to dgnd analog voltage powers up first digital voltage powers up first MCP41HVX1 ds20005207a-page 24 ? 2013 microchip technology inc. figure 4-2: voltage ranges. v- and dgnd v+ v l case 1 v- v+ dgnd case 2 v- v+ and v l dgnd case 3 v l anywhere between v+ and v- high- voltage range high- voltage range high- voltage range (v l ? dgnd) ? 2013 microchip technology inc. ds20005207a-page 25 MCP41HVX1 4.2 por/bor operation the resister network?s devices are powered by the analog power signals (v+ / v-), but the digital logic (including the wiper registers) is powered by the digital power signals (v l / dgnd). so, both the digital circuitry and analog circuitry have independent por/bor circuits. the wiper position will be forced to the default state when the v+ voltage (relative to v-) is above the analog por/bor trip point. the wiper register will be in the default state when the v l voltage (relative to dgnd) is above the digital por/bor trip point. the digital-signal-to-analog-signal voltage level shifters require a minimum voltage between the v l and v- signals. this voltage requirement is below the operating supply voltage specifications. the wiper output may fluctuate while the v l voltage is less than the level shifter operating voltage, since the analog values may not reflect the digital value. output issues may be reduced by powering-up the digital supply voltages to their operating voltage, before powering the analog supply voltage. 4.2.1 power-on reset each power system has its own independent power- on-reset circuitry. this is done so that regardless of the power-up sequencing of the analog and digital power rails, the wiper output will be forced to a default value after minimum conditions are meet for either power supply. table 4-1 shows the interaction between the analog and digital pors for the v+ and v l voltages on the wiper pin state. table 4-1: wiper pin state based on por conditions 4.2.1.1 digital circuitry the digital power-on reset (dpor) is the case where the device?s v l signal has power applied (referenced from dgnd) and the voltage rises above the trip point. the brown-out reset (bor) occurs when a device had power applied to it, and the voltage drops below the trip point. the device?s ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). the maximum v por /v bor voltage is less then 1.8v. when the device powers up, the device v l will cross the v por /v bor voltage. once the v l voltage crosses the v por /v bor voltage, the following happens: ? volatile wiper registers are loaded with the por/ bor value ? the tcon registers are loaded with the default values ? the device is capable of digital operation table 4-2 shows the default por/bor wiper register setting selection. when v por /v bor < v dd < 2.7v, the electrical performance may not meet the data sheet specifications. in this region, the device is capable of incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed. table 4-2: default por/bor wiper register setting (digital) v l voltage v+ voltage comments v+ < v apor v+ ? v apor v l < v dpor unknown mid-scale v l ? v dpor unknown wiper register value ( 1 ) wiper register can be updated note 1: default por state of the wiper register value is the mid-scale value. typical r ab value package code default por wiper register setting device resolution wiper code 5.0 k ? -502 mid-scale 8-bit 7fh 7-bit 3fh 10.0 k ? -103 mid-scale 8-bit 7fh 7-bit 3fh 50.0 k ? -503 mid-scale 8-bit 7fh 7-bit 3fh 100.0 k ? -104 mid-scale 8-bit 7fh 7-bit 3fh note 1: register setting independent of analog power voltage. MCP41HVX1 ds20005207a-page 26 ? 2013 microchip technology inc. 4.2.1.2 analog circuitry the analog power-on reset (apor) is the case where the device?s v+ pin voltage has power applied (refer- enced from v-) and the v+ pin voltage rises above the trip point. once the v l pin voltage exceeds the digital por trip point voltage, the wiper register will control the wiper setting. table 4-3 shows the default por/bor wiper setting for when the v l pin is not powered (< digital por trip point). table 4-3: default por/bor wiper setting (analog) figure 4-3: dgnd, v l , v+, and v- signal waveform examples. typical r ab value package code default por wiper setting device resolution 5.0 k ? -502 mid-scale 8-bit 7-bit 10.0 k ? -103 mid-scale 8-bit 7-bit 50.0 k ? -503 mid-scale 8-bit 7-bit 100.0 k ? -104 mid-scale 8-bit 7-bit note 1: wiper setting is dependent on the wiper register value if the v l voltage is greater than the digital por voltage. v- v+ v l referenced to dgnd v por / v bor dgnd brown-out condition wiper value unknown digital logic has been reset (por). this includes the wiper register. digital logic has been reset (por). this includes the wiper register. analog power is recovering (still low) and v l digital logic has been reset (por). this includes the wiper register. brown-out condition, wiper value unknown analog power is low note: when v l is above v+ (floating), the v l pin esd clamping diode will cause the v+ level to be pulled up. rail/pin no longer sources current to v+ ? 2013 microchip technology inc. ds20005207a-page 27 MCP41HVX1 4.2.2 brown-out reset each power system has its own independent brown- out-reset circuitry. this is done so that regardless of the power-down sequencing of the analog and digital power rails, the wiper output will be forced to a default value after the low voltage conditions are meet for either power supply. table 4-4 shows the interaction between the analog and digital bors for the v+ and v l voltages on the wiper pin state. table 4-4: wiper pin state based on bor conditions 4.2.2.1 digital circuitry when the device?s digital power supply powers down, the device v l pin voltage will cross the digital v dpor / v dbor voltage. once the v l voltage decreases below the v dpor / v dbor voltage, the following happens: ? serial interface is disabled if the v l voltage decreases below the v ram voltage the following happens: ? volatile wiper registers may become corrupted ? tcon registers may become corrupted section 4.2.1, power-on reset describes what occurs as the voltage recovers above the v dpor / v dbor voltage. serial commands not completed due to a brown-out condition may cause the memory location to become corrupted. the brown-out circuit establishes a minimum v dbor threshold for operation (v dbor < 1.8v). the digital bor voltage (v dbor ) is higher then the ram retention voltage (v ram ) so that as the device voltage crosses the digital bor threshold, the value that is loaded into the volatile wiper register is not corrupted, due to ram retention issues. when v l < v dbor , all communications are ignored and potentiometer terminals are forced to the analog bor state. whenever v l transitions from v l < v dbor to v l > v dbor , (a por event) the wiper?s por/bor value is latched into the wiper register and the volatile tcon register is forced to the por/bor state. when 1.8v ? v l , the device is capable of digital operation. table 4-5 shows the digital potentiometer?s level of functionality across the entire v l range, while figure 4- 4 illustrates the power-up and brown-out functionality. 4.2.2.2 analog circuitry the analog brown-out-reset (abor) is the case where the device?s v+ pin has power applied (refer- enced from v-) and the v+ pin voltage drops below the trip point. in this case, the resistor network terminals pins can become an unknown state. v l voltage v+ voltage comments v+ < v abor v+ ? v abor v l < v dbor unknown mid-scale v l ? v dbor unknown wiper register value ( 1 ) wiper register can be updated note 1: default por state of the wiper register value is the mid-scale value. MCP41HVX1 ds20005207a-page 28 ? 2013 microchip technology inc. table 4-5: device functionality at each v l region figure 4-4: power-up and brown out - v+ / v- at normal operating voltage. v l level v+ / v- level serial interface potentiometer terminals ( 2 ) wiper comment register setting output ( 2 ) v l < v dbor < 1.8v valid range ignored ?unknown? unknown invalid invalid range ignored ?unknown? unknown invalid v dbor ? v l < 1.8v valid range ?unknown? connected volatile wiper register initialized valid the volatile registers are forced to the por/bor state when v l transitions above the v dpor trip point invalid range ?unknown? connected invalid 1.8v ? v l ? 5.5v valid range accepted connected volatile wiper register determines wiper setting valid invalid range accepted connected invalid note 1: for system voltages below the minimum operating voltage, it is recommended to use a voltage supervisor to hold the system in reset. this ensures that MCP41HVX1 commands are not attempted out of the oper- ating range of the device. 2: assumes that v+ > v apor . v por/bor dgnd v l outside specified normal operation range device?s serial wiper forced to default por/bor setting v bor delay normal operation range 1.8v interface is ?not operational? ac/dc range v ram device?s serial interface is ?not specified ? 2013 microchip technology inc. ds20005207a-page 29 MCP41HVX1 4.3 control module the control module controls the following functionality: ? shutdown ? wiper latch 4.3.1 shutdown the MCP41HVX1 has two methods to disconnect the terminal?s pins (p0a, p0w, and p0b) from the resistor network. these are: ? hardware shutdown pin (shdn ) ? terminal control register (tcon) 4.3.1.1 hardware shutdown pin operation the shdn pin has the same functionality as microchip?s family of standard voltage devices. when the shdn pin is low, the p0a terminal will disconnect (become open) while the p0w terminal simultaneously connect to the p0b terminal (see figure 4-5 ). the hardware shutdown pin mode does not corrupt the volatile wiper register. so when shutdown is exited, the device returns to the wiper setting specified by the volatile wiper value. see section 5.7 for additional description details. figure 4-5: hardware shutdown resistor network configuration. 4.3.1.2 terminal control register the terminal control (tcon) register allows the device?s terminal pins to be independently removed from the application circuit. these terminal control settings do not modify the wiper setting values. also this has no effect on the serial interface and the memory/wipers are still under full user control. the resistor network has four tcon bits associated with it. one bit for each terminal (a, w, and b) and one to have a software configuration that matches the configuration of the shdn pin. these bits are named r0a, r0w, r0b, and r0hw. register 4-1 describes the operation of the r0hw, r0a, r0b, and r0w bits. figure 4-6 shows how the shdn pin signal and the r0hw bit signal interact to control the hardware shutdown of each resistor network (independently). figure 4-6: r0hw bit and shdn pin interaction. note: when the shdn pin is active (v il ), the state of the tcon register bits is overridden (ignored). when the state of the shdn pin returns to the inactive state (v ih ), the tcon register bits return to controlling the terminal connection state. that is the value in the tcon register is not corrupted note: when the shdn pin is active, the serial interface is not disabled, and serial inter- face activity is executed. a b w resistor network note: when the r0hw bit forces the resistor network into the hardware shdn state, the state of the tcon register r0a, r0w, and r0b bits is overridden (ignored). when the state of the r0hw bit no longer forces the resistor network into the hardware shdn state, the tcon register r0a, r0w, and r0b bits return to controlling the terminal connection state. that is, the r0hw bit does not corrupt the state of the r0a, r0w, and r0b bits. shdn (from pin) r0hw (from tcon register) to pot 0 hardware shutdown control MCP41HVX1 ds20005207a-page 30 ? 2013 microchip technology inc. 4.3.2 wiper latch the wiper latch pin is used to control when the new wiper value in the wiper register is transferred to the wiper. this is useful for applications that need to synchronize the wiper updates. this may be for synchronization to an external event, such as zero crossing, or to synchronize the update of multiple digital potentiometers. when the wlat pin is high, transfers from the wiper register to the wiper are inhibited. when the wlat pin is low, transfers may occur from the wiper register to the wiper. figure 4-7 shows the interaction of the wlat pin and the loading of the wiper. if the external event crossing time is long, then the wiper could be updated the entire time that the wlat signal is low. once the wlat signal goes high, the transfer from the wiper register is disabled. the wiper register can continue to be updated. only the cs pin is used to enable/disable serial commands. if the application does not require synchronized wiper register updates, then the wlat pin should be tied low. 4.3.3 device current modes there are two current modes for volatile devices. these are: ? serial interface inactive (static operation) ? serial interface active for the spi interface, static operation occurs when the cs pin is at the v ih voltage and the sck pin is static (high or low). figure 4-7: wlat interaction with wiper during serial communication - (spi mode 1,1). note 1: this feature only inhibits the data transfer from the wiper register to the wiper. 2: when the wlat pin becomes active, data transferred to the wiper will not be corrupted due to the wiper register buf- fer getting loaded from an active spi command. cs sck wiper register v ih v il wlat v ih v il loaded wiper register transferred 16 sck 16 sck 16 sck 16 sck when wlat goes low during an spi active transfer, the previously loaded wiper register value is when wlat goes high during an spi active transfer, the wiper register value will be updated with the new value from this serial command when the command completes. the wiper will retain the transferred to the wiper. ( 1 ) v il to wiper note 1: the wiper register may be updated on 16 sck cycles for a write command, or on 8 sck cycles with an increment or decrement command. value that was last transferred from the wiper register before the w lat pin went high. 2: the wlat pin should not be brought high during the falling edge of the 8th clock cycle of an increment or decrement command or the 16th clock cycle of a write command. ? 2013 microchip technology inc. ds20005207a-page 31 MCP41HVX1 4.4 memory map the device memory supports 16 locations that are 8- bits wide (16x8 bits). this memory space contains only volatile locations (see ta b l e 4 - 7 ). 4.4.1 volatile memory (ram) there are two volatile memory locations. these are: ? volatile wiper 0 ? terminal control (tcon0) register 0 the volatile memory starts functioning at the ram retention voltage (v ram ). the por/bor wiper code is shown in tab l e 4 - 6 . table 4-7 shows this memory map and which serial commands operate (and don?t) on each of these locations. accessing an ?invalid? address (for that device) or an invalid command for that address will cause an error condition (cmderr) on the serial interface. 4.4.1.1 write to invalid (reserved) addresses any write to a reserved address will be ignored and will generate an error condition. to exit the error condition, the user must take the cs pin to the v ih level and then back to the active state (v il ). table 4-7: memory map and the supported commands table 4-6: wiper por standard settings resistance code typical r ab value default por wiper setting wiper code 8-bit 7-bit -502 5.0 k ? mid scale 7fh 3fh -103 10.0 k ? mid scale 7fh 3fh -503 50.0 k ? mid scale 7fh 3fh -104 100.0 k ? mid scale 7fh 3fh address function allowed commands disallowed commands ( 1 ) memory type 00h volatile wiper 0 read, write, increment, decrement ?ram 01h - 03h reserved none read, write, increment, decrement ? 04h volatile tcon register read, write increment, decrement ram 05h - 0fh reserved none read, write, increment, decrement ? note 1: this command on this address will generate an error condition. to exit the error condition, the user must take the cs pin to the v ih level and then back to the active state (v il ). MCP41HVX1 ds20005207a-page 32 ? 2013 microchip technology inc. 4.4.1.2 terminal control (tcon) registers the terminal control (tcon) register contains 4 control bits for wiper 0. register 4-1 describes each bit of the tcon register. the state of each resistor network terminal connection is individually controlled. that is, each terminal connection (a, b and w) can be individually connected/ disconnected from the resistor network. this allows the system to minimize the currents through the digital potentiometer. the value that is written to this register will appear on the resistor network terminals when the serial command has completed. on a por/bor, these registers are loaded with ffh, for all terminals connected. the host controller needs to detect the por/bor event and then update the volatile tcon register values. register 4-1: tcon0 bits ( 1 ) (continued) r-1 r-1 r-1 r-1 r/w-1 r/w-1 r/w-1 r/w-1 d7 d6 d5 d4 r0hw r0a r0w r0b bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7:4 d7-d4: reserved. forced to ? 1 ? bit 3 r0hw: resistor 0 hardware configuration control bit this bit forces resistor 0 into the ?shutdown? configuration of the hardware pin 1 = resistor 0 is not forced to the hardware pin ?shutdown? configuration 0 = resistor 0 is forced to the hardware pin ?shutdown? configuration bit 2 r0a: resistor 0 terminal a (p0a pin) connect control bit this bit connects/disconnects the resistor 0 terminal a to the resistor 0 network 1 = p0a pin is connected to the resistor 0 network 0 = p0a pin is disconnected from the resistor 0 network bit 1 r0w: resistor 0 wiper (p0w pin) connect control bit this bit connects/disconnects the resistor 0 wiper to the resistor 0 network 1 = p0w pin is connected to the resistor 0 network 0 = p0w pin is disconnected from the resistor 0 network bit 0 r0b: resistor 0 terminal b (p0b pin) connect control bit this bit connects/disconnects the resistor 0 terminal b to the resistor 0 network 1 = p0b pin is connected to the resistor 0 network 0 = p0b pin is disconnected from the resistor 0 network note 1: these bits do not affect the wiper register values. 2: the hardware shdn pin (when active) overrides the state of these bits. when the shdn pin returns to the inactive state, the tcon register will control the state of the terminals. the shdn pin does not modify the state of the tcon bits. ? 2013 microchip technology inc. ds20005207a-page 33 MCP41HVX1 5.0 resistor network the resistor network has either 7-bit or 8-bit resolution. each resistor network allows zero scale to full-scale connections. figure 5-1 shows a block diagram for the resistive network of a device. the resistor network has up to three external connections. these are referred to as terminal a, terminal b, and the wiper (or terminal w). the resistor network is made up of several parts. these include: ? resistor ladder module ? wiper ? shutdown control (terminal connections) terminal a and b as well as the wiper w do not have a polarity. these terminals can support both positive and negative current. figure 5-1: resistor block diagram. 5.1 resistor ladder module the r ab resistor ladder is composed of the series of equal value step resistors (r s ) and the full-scale (r fs ) and zero-scale (r zs ) resistances: r ab = r zs + n * r s + r fs where ?n? is determined by the resolution of the device. the r fs and r zs resistances are discussed in section 5.1.3 . there is a connection point (tap) between each r s resistor. each tap point is a connection point for an analog switch. the opposite side of the analog switch is connected to a common signal which is connected to the terminal w (wiper) pin (see section 5.2 ). figure 5-1 shows a block diagram of the resistor network. the r ab (and r s ) resistance has small variations over voltage and temperature. the end points of the resistor ladder are connected to analog switches, which are connected to the device terminal a and terminal b pins. in the ideal case, these switches would have 0 ? of resistance, that is r fs =r zs =0 ? . this will also be referred as the simplified model. for an 8-bit device, there are 255 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 255 resistors, thus provid- ing 256 possible settings (including terminal a and terminal b). a wiper setting of 00h connects terminal w (wiper) to terminal b (zero scale). a wiper setting of 7fh is the mid-scale setting. a wiper setting of ffh con- nects terminal w (wiper) to terminal a (full scale). table 5-2 illustrates the full wiper setting map. for a 7-bit device, there are 127 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 127 resistors, thus provid- ing 128 possible settings (including terminal a and terminal b). a wiper setting of 00h connects terminal w (wiper) to terminal b (zero scale). a wiper setting of 3fh is the mid-scale setting. a wiper setting of 7fh con- nects the wiper to terminal a (full scale). ta b l e 5 - 2 illustrates the full wiper setting map. 5.1.1 r ab current (i rab ) the current through the r ab resistor (a pin to b pin) is dependent on the voltage on the v a and v b pins and the r ab resistance. equation 5-1: r ab r s a r s r s r s b 255 254 253 1 0 r w (1) w (01h) analog mux r w (1) (00h) r w (1) (fdh) r w (1) (feh) r w (1) (ffh) note 1: the wiper resistance is dependent on several factors including wiper code, device v+ voltage, terminal voltages (on a, b and w), and temperature. also for the same conditions, each tap selection resistance has a small variation. this r w variation has greater effect on some specifications (such as inl) for the smaller resistance devices (5.0 k ? ) compared to larger resistance devices (100.0 k ? ). r ab 8-bit n = 127 126 125 1 0 (01h) (00h) (7dh) (7eh) (7fh) 7-bit n = r fs r s r zs r ab = r zs + ( n * r s ) + r fs = | (v a - v b ) | (i rab ) v a is the voltage on the v a pin. v b is the voltage on the v b pin. i rab is the current into the v ref pin. MCP41HVX1 ds20005207a-page 34 ? 2013 microchip technology inc. 5.1.2 step resistance (r s ) step resistance (r s ) is the resistance from one tap set- ting to the next. this value will be dependent on the r ab value that has been selected (and the full scale and zero scale resistances). the r s resistors are manufactured so that they should be very consistent with each other, and track each other?s values as voltage and/or temperature change. equation 5-2 shows the simplified and detailed equa- tions for calculating the r s value. the simplified equa- tion assumes r fs =r zs =0 ? . ta b l e 5 - 1 shows example step resistance calculations for each device, and the variation of the detailed model (r fs ? 0 ? ; r zs ? 0 ? ) from the simplified model (r fs =r zs = 0 ? ). as the r ab resistance option increases, the effects of the r zs and r fs resistance decreases. the total resistance of the device has minimal variation due to operating voltage (see device characterization graphs). equation 5-2 shows calculations for the step resistance. equation 5-2: r s calculation table 5-1: example step resistances (r s ) calculations simplified model (assumes r fs = r zs = 0 ? ) r ab = ( n * r s ) detailed model r ab = r fs + ( n * r s ) + r zs r s = r ab n r s = r ab - r fs - r zs n where: 8-bit 7-bit r ab 255 r ab 127 r s = r s = or r s = (v fs - v zs ) n i ab ?n? = 255 (8-bit) or 127 (7-bit) v fs is the wiper voltage at full-scale code v zs is the wiper voltage at zero-scale code i ab is the current between terminal a and terminal b example resistance ( ? ) variation % ( 1 ) resolution comment r ab r zs ( 3 ) r fs ( 3 ) r s equation value 5,000 0 0 5,000 / 127 39.37 0 7-bit (127 r s ) simplified model ( 2 ) 80 60 4,860 / 127 38.27 -2.80 0 0 5,000 / 255 19.61 0 8-bit (255 r s ) simplified model ( 2 ) 80 60 4,860 / 255 19.06 -2.80 10,000 0 0 10,000 / 127 78.74 0 7-bit (127 r s ) simplified model ( 2 ) 80 60 9,860 / 127 77.64 -1.40 0 0 10,000 / 255 39.22 0 8-bit (255 r s ) simplified model ( 2 ) 80 60 9,860 / 255 38.67 -1.40 50,000 0 0 50,000 / 127 393.70 0 7-bit (127 r s ) simplified model ( 2 ) 80 60 49,860 / 127 392.60 -0.28 0 0 50,000 / 255 196.08 0 8-bit (255 r s ) simplified model ( 2 ) 80 60 49,860 / 255 195.53 -0.28 100,000 0 0 100,000 / 127 787.40 0 7-bit (127 r s ) simplified model ( 2 ) 80 60 99,860 / 127 786.30 -0.14 0 0 100,000 / 255 392.16 0 8-bit (255 r s ) simplified model ( 2 ) 80 60 99,860 / 255 391.61 -0.14 note 1: delta % from simplified model r s calculation value: 2: assumes r fs =r zs =0 ? . 3: zero-scale (r zs ) and full-scale (r fs ) resistances are dependent on many operational characteristics of the device, including the v+ / v- voltage, the voltages on the a, b and w terminals, the wiper code selected, the r ab resistance, and the temperature of the device. ? 2013 microchip technology inc. ds20005207a-page 35 MCP41HVX1 5.1.3 r fs and r zs resistors the r fs and r zs resistances are artifacts of the r ab resistor network implementation. in the ideal model, the r fs and r zs resistances would be 0 ? . these resistors are included in the block diagram to help better model the actual device operation. equation 5-3 shows how to estimate the r s , r fs , and r zs resistances, based on the measured voltages of v ref , v fs , and v zs and the measured current i vref . equation 5-3: estimating r s , r fs , and r zs 5.2 wiper the wiper terminal is connected to an analog switch mux, where one side of all the analog switches are connected together, the w terminal. the other side of each analog switch is connected to one of the taps of the r ab resistor string (see figure 5-1 ). the value in the volatile wiper register selects which analog switch to close, connecting the w terminal to the selected node of the resistor ladder. the wiper register is 8-bits wide, and ta bl e 5 - 2 shows the wiper value state for both 7-bit and 8-bit devices. the wiper resistance (r w ) is the resistance of the selected analog switch in the analog mux. this resistance is dependent on many operational characteristics of the device, including the v+ / v- volt- age, the voltages on the a, b and w terminals, the wiper code selected, the r ab resistance, and the tem- perature of the device. when the wiper value is at zero scale (00h), the wiper is connected closest to the b terminal. when the wiper value is at full scale (ffh for 8-bit, 7fh for 7-bit), the wiper is connected closest to the a terminal. a zero-scale wiper value connects the w terminal (wiper) to the b terminal (wiper = 00h). a full-scale wiper value connects the w terminal (wiper) to the a terminal (wiper = ffh (8-bit), or wiper = 7fh (7-bit)). in these configurations, the only resistance between the terminal w and the other terminal (a or b) is that of the analog switches. table 5-2: volatile wiper value vs. wiper position v fs is the v w voltage when the wiper code is at full-scale. v zs is the v w voltage when the wiper code is at zero-scale. r fs = | ( v a - v fs ) | (i rab ) r zs = | ( v zs - v b ) | (i rab ) v s = ( v fs - v zs ) 255 where: r s = v s (i rab ) (8-bit device) v s = ( v fs - v zs ) 127 (7-bit device) wiper setting properties 7-bit 8-bit 7fh ffh full scale (w = a), increment commands ignored 7eh - 40h feh - 80h w = n 3fh 7fh w = n (mid scale) 3eh - 01h 7eh - 01h w = n 00h 00h zero scale (w = b) decrement command ignored MCP41HVX1 ds20005207a-page 36 ? 2013 microchip technology inc. 5.2.1 wiper resistance (r w ) wiper resistance is significantly dependent on: ? the resistor network?s supply voltage (v rn ) ? the resistor network?s terminal (a, b, and w) voltages ? switch leakage (occurs at higher temperatures) ?i w current figure 5-2 show the wiper resistance characterization data for all four r ab resistances and temperatures. each r ab resistance determined the maximum wiper current based on worst case conditions r ab =r ab maximum and at full scale code, v bw ~= v+ (but not exceeding v+). the v+ targets were 10v, 20v, and 36v. what this graph shows is that at higher r ab resistances (50 k ? and 100 k ? ) and at the highest tem- perature (+125c), the analog switch leakage causes a increase in the measured result of r w . where r w is measured in a rheostat configuration with r w = (v bw - v ba ) / i bw . figure 5-2: r w resistance vs r ab , wiper current (i w ), temperature and wiper code. since there is minimal variation of the total device resistance (r ab ) over voltage, at a constant tempera- ture (see device characterization graphs), the change in wiper resistance over voltage can have a significant impact on the r inl and r dnl errors. 5.2.2 potentiometer configuration in a potentiometer configuration, the wiper resistance variation does not effect the output voltage seen on the w pin and therefore is not a significant source of error. 5.2.3 rheostat configuration in a rheostat configuration, the wiper resistance varia- tion creates nonlinearity in the r bw (or r aw ) value. the lower the nominal resistance (r ab ), the greater the possible relative error. also a change in voltage needs to be taken into account. for the 5.0 k ? device the maximum wiper resistance at 5.5v is approximately 6% of the total resistance, while at 2.7v it is approximately 6.5% of the total resistance. 5.2.4 level shifters (digital to analog) since the digital logic may operate anywhere within the analog power range, level shifters are present so that the digital signals control the analog circuitry. this level shifter logic is relative to the v- and v l voltages. a delta voltage of 2.7v between v l and v- is required for the serial interface to operate at the maximum specified frequency. 800 1000 1200 1400 1600 1800 2000 2200 2400 e sistance r w ( : ) r 40c 5k iw = 1.7ma +25c 5k iw = 1.7ma +85c 5k iw = 1.7ma +125c 5k iw = 1.7ma r 40c 5k iw = 3.3ma +25c 5k iw = 3.3ma +85c 5k iw = 3.3ma +125c 5k iw = 3.3ma r 40c 5k iw =6.0ma +25c 5k iw = 6.0ma +85c 5k iw = 6.0ma +125c 5k iw = 6.0ma r 40c 10k iw = 830ua +25c 10k iw = 830ua +85c 10k iw = 830ua +125c 10k iw = 830ua r 40c 10k iw = 1.7ma +25c 10k iw = 1.7ma +85c 10k iw = 1.7ma +125c 10k iw = 1.7ma r 40c 10k iw = 3.0ma +25c 10k iw = 3.0ma +85c 10k iw = 3.0ma +125c 10k iw = 3.0ma r 40c 50k iw = 170ua +25c 50k iw = 170ua +85c 50k iw = 170ua +125c 50k iw = 170ua r 40c 50k iw = 330ua +25c 50k iw = 330ua +85c 50k iw = 330ua +125c 50k iw = 330ua r 40c 50k iw = 600ua +25c 50k iw = 600ua +85c 50k iw = 600ua +125c 50k iw = 600ua r 40c 100k iw = 83ua +25c 100k iw = 83ua +85c 100k iw = 83ua +125c 100k iw = 83ua r 40c 100k iw =170ua +25c 100k iw = 170ua +85c 100k iw = 170ua +125c 100k iw = 170ua r 40c 100k iw = 300ua +25c 100k iw = 300ua +85c 100k iw = 300ua +125c 100k iw = 300ua i w = 83ua, +125c (100k : ) increased wiper resistance (r w ) occurs due to increased analog switch leakage at higher temperatures (such as +125c) and larger r resistances 0 200 400 600 800 0 32 64 96 128 160 192 224 256 wiper r e dac wiper code i w = 170ua, +125c (100k : ) i w = 170ua, +125c (50k : ) i w = 300ua, +125c (100k : ) larger r ab resistances . ? 2013 microchip technology inc. ds20005207a-page 37 MCP41HVX1 5.3 terminal currents the terminal currents are limited by several factors, including the r ab resistance (r s resistance). the maximum current occurs when the wiper is at either the zero-scale (i bw ) or full-scale (i aw ) code. in this case, the current is only going through the analog switches (see i t specification in electrical characteristics ). when the current passes through at least one r s resistive element, then the maximum terminal current (i t ) has a different limit. the current through the r ab resistor is limited by the r ab resistance. the worst case (max current) occurs when the resistance is at the minimum r ab value. higher current capabilities allow a greater delta voltage between the desired terminals for a given resistance. this also allows a more usable range of wiper code val- ues, without violating the maximum terminal current specification. ta bl e 5 - 3 shows resistance and current calculations based on the r ab resistance (r s resis- tance) for a system that supports 18v ( ? 36v). in rheostat configuration, the minimum wiper-code value is shown (for v bw = 36v). as the v bw voltage decreases, the minimum wiper-code value also decreases. using a wiper code less then this value will cause the maximum terminal current (i t ) specification to be violated. table 5-3: terminal (wiper) current and wiper settings (r w = r fs = r zs = 0 ? ) note: for high terminal-current applications, it is recommended that proper pcb layout techniques be used to address the thermal implications of this high current. the qfn package has better thermal properties than the tssop package. r ab resistance ( ? )r s(min) ( ? ) i ab(max) (ma) (= 36v / r ab(min) ) ( 1 ) i t (a, b, or w (i w ) ) (ma) (i bw(w = zs) , i aw(w = fs ) ( 1 ) r bw ( ? ) (= 36v / i t(max) ) ( 2 ) rheostat min ?n? when v bw = 36v n * r s(min) * 36v ??????? i t (ma) ( 3 ) rheostat v bw(max) when wiper = 01h (v) (= i t(max) * r s(min) ) typical min max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 5,000 4,000 6,000 15.686 31.496 9.00 25.0 1,440 91 45 0.392 0.787 10,000 8,000 12,000 31.373 62.992 4.50 12.5 2,880 91 45 0.392 0.787 50,000 40,000 60,000 156.863 314.961 0.90 6.5 5539 35 17 1.020 2.047 100,000 80,000 120,000 313.725 629.9 0.45 6.5 5539 17 8 2.039 4.094 note 1: i bw or i aw currents can be much higher then this depending on voltage differential between terminal b and terminal w or terminal a and terminal w. 2: any r bw resistance greater then this limits the current. 3: if v bw = 36v, then the wiper code value must be greater than or equal to min ?n?. wiper codes less than min ?n? will cause the wiper current (i w ) to exceed the specification. wiper codes greater than min ?n? will cause the wiper current to be less then the maximum. the min ?n? number has been rounded up from the calculated number to ensure that the wiper current does not exceed the maximum specification. MCP41HVX1 ds20005207a-page 38 ? 2013 microchip technology inc. figure 5-3 through figure 5-6 show a graph of the cal- culated currents (minimum, typical, and maximum) for each resistor option. these graphs are based on 25 ma (5 k ? ), 12.5 ma (10 k ? ), and 6.5 ma (50 k ? and 100 k ? ) specifications. to ensure no damage to the resistor network (including long-term reliability) the maximum terminal current must not be exceeded. this means that the application must assume that the r ab resistance is the minimum r ab value (r ab(min) , see blue lines in graphs). looking at the 50 k ? device, the maximum terminal current is 6.5 ma. that means that any wiper code value greater than 36 ensures that the terminal current is less than 6.5 ma. this is ~14% of the full scale value. if the application could change to the 100 k ? device, which has the same maximum terminal current specifi- cation, any wiper-code value greater than 18 ensures that the terminal current is less than 6.5 ma. this is ~7% of the full-scale value. supporting higher terminal current allows a greater wiper code range for a given v bw voltage. figure 5-3: maximum i bw vs wiper code - 5 k ? . figure 5-4: maximum i bw vs wiper code - 10 k ? . figure 5-5: maximum i bw vs wiper code - 50 k ? . figure 5-6: maximum i bw vs wiper code - 100 k ? . figure 5-7 shows a graph of the maximum v bw voltage vs wiper code (for 5 k ? and 10 k ? devices). to ensure that no damage is done to the resistor network, the r ab(min) resistance (blue line) should be used to deter- mine v bw voltages for the circuit. devices where the r ab resistance is greater than the r ab(min) resistance will naturally support a higher voltage limit. figure 5-7: maximum v bw vs wiper code (5 k ? and 10 k ? devices). r ab = 5k : 000.0e+0 5.0e-3 10.0e-3 15.0e-3 20.0e-3 25.0e-3 30.0e-3 0 32 64 96 128 160 192 224 256 wiper code i bw(max) (a) r a b(max) r ab(typ) r a b(min) r ab = 10k : 000.0e+0 2.0e-3 4.0e-3 6.0e-3 8.0e-3 10.0e-3 12.0e-3 14.0e-3 0 32 64 96 128 160 192 224 256 wiper code i bw(max) (a) r a b(max) r ab(typ) r a b(min) 7.0e-3 r ab = 50k : 50e 3 6.0e-3 7.0e-3 r ab = 50k : r ab(min) 4.0e-3 5.0e-3 6.0e-3 7.0e-3 a x) (a) r ab = 50k : r ab(typ) r ab(min) 20e 3 3.0e-3 4.0e-3 5.0e-3 6.0e-3 7.0e-3 i bw(max) (a) r ab = 50k : r ab(typ) r ab(min) 1.0e-3 2.0e-3 3.0e-3 4.0e-3 5.0e-3 6.0e-3 7.0e-3 i bw(max) (a) r ab = 50k : r ab(max) r ab(typ) r ab(min) 000.0e+0 1.0e-3 2.0e-3 3.0e-3 4.0e-3 5.0e-3 6.0e-3 7.0e-3 0 32 64 96 128 160 192 224 256 i bw(max) (a) wiper code r ab = 50k : r ab(max) r ab(typ) r ab(min) 000.0e+0 1.0e-3 2.0e-3 3.0e-3 4.0e-3 5.0e-3 6.0e-3 7.0e-3 0 32 64 96 128 160 192 224 256 i bw(max) (a) wiper code r ab = 50k : r ab(max) r ab(typ) r ab(min) 7.0e-3 r ab = 100k : 50e 3 6.0e-3 7.0e-3 r ab = 100k : r ab(min) 4.0e-3 5.0e-3 6.0e-3 7.0e-3 a x) (a) r ab = 100k : r ab(typ) r ab(min) 20e 3 3.0e-3 4.0e-3 5.0e-3 6.0e-3 7.0e-3 i bw(max) (a) r ab = 100k : r ab(typ) r ab(min) 1.0e-3 2.0e-3 3.0e-3 4.0e-3 5.0e-3 6.0e-3 7.0e-3 i bw(max) (a) r ab = 100k : r ab(max) r ab(typ) r ab(min) 000.0e+0 1.0e-3 2.0e-3 3.0e-3 4.0e-3 5.0e-3 6.0e-3 7.0e-3 0 32 64 96 128 160 192 224 256 i bw(max) (a) wiper code r ab = 100k : r ab(max) r ab(typ) r ab(min) 000.0e+0 1.0e-3 2.0e-3 3.0e-3 4.0e-3 5.0e-3 6.0e-3 7.0e-3 0 32 64 96 128 160 192 224 256 i bw(max) (a) wiper code r ab = 100k : r ab(max) r ab(typ) r ab(min) 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 0 32 64 96 128 160 192 224 256 wiper code v bw(max) (v) r ab(max) r ab(typ) r a b(min) ? 2013 microchip technology inc. ds20005207a-page 39 MCP41HVX1 table 5-4 shows the maximum v bw voltage that can be applied across the terminal b to terminal w pins for a given wiper code value (for the 5 k ? and 10 k ? devices). these calculations assume the ideal model (r w =r fs =r zs =0 ? ) and show the calculations based on r s(min) and r s(max) . tab l e 5 - 5 shows the same calculations for the 50 k ? devices, and table 5-6 shows the calculations for the 100 k ? devices. these tables are supplied as a quick reference. table 5-4: max v bw at each wiper code (r w = r fs = r zs = 0 ? ) for v+ - v- = 36v, 5k ? and 10k ? devices. code v bw(max) code v bw(max) code v bw(max) hex dec r s(min) r s(max) hex dec r s(min) r s(max) hex dec r s(min) r s(max) 00h 0 0.000 0.000 20h 32 12.549 18.824 40h 64 25.098 01h 1 0.392 0.588 21h 33 12.941 19.412 41h 65 25.490 02h 2 0.784 1.176 22h 34 13.333 20.000 42h 66 25.882 03h 3 1.176 1.765 23h 35 13.725 20.588 43h 67 25.275 04h 4 1.569 2.353 24h 36 14.118 21.176 44h 68 26.667 05h 5 1.961 2.941 25h 37 14.510 21.765 45h 69 27.059 06h 6 2.353 3.529 26h 38 14.902 22.353 46h 70 27.451 07h 7 2.745 4.118 27h 39 15.294 22.941 47h 71 27.843 08h 8 3.137 4.706 28h 40 15.686 23.529 48h 72 28.235 09h 9 3.529 5.294 29h 41 16.078 24.118 49h 73 28.627 0ah 10 3.922 5.882 2ah 42 16.471 24.706 4ah 74 29.020 0bh 11 4.314 6.471 2bh 43 16.863 25.294 4bh 75 29.412 0ch 12 4.706 7.059 2ch 44 17.255 25.882 4ch 76 29.804 0dh 13 5.098 7.647 2dh 45 17.647 26.471 4dh 77 30.196 0eh 14 5.490 8.235 2eh 46 18.039 27.059 4eh 78 30.588 0fh 15 5.882 8.824 2fh 47 18.431 27.647 4fh 79 30.980 10h 16 5.275 9.412 30h 48 18.824 28.235 50h 80 31.373 11h 17 6.667 10.000 31h 49 19.216 28.824 51h 81 31.765 12h 18 7.059 10.588 32h 50 19.608 29.412 52h 82 32.157 13h 19 7.451 11.176 33h 51 20.000 30.000 53h 83 32.549 14h 20 7.843 11.765 34h 52 20.392 30.588 54h 84 32.941 15h 21 8.235 12.353 35h 53 20.784 31.176 55h 85 33.333 16h 22 8.627 12.941 36h 54 21.176 31.765 56h 86 33.725 17h 23 9.020 13.529 37h 55 21.569 32.353 57h 87 34.118 18h 24 9.412 14.118 38h 56 21.961 32.941 58h 88 34.510 19h 25 9.804 14.706 39h 57 22.353 33.529 59h 89 34.902 1ah 26 10.196 15.294 3ah 58 22.745 34.118 5ah 90 35.294 1bh 27 10.588 15.882 3bh 59 23.137 34.706 5bh 91 35.686 1ch 28 10.980 16.471 3ch 60 23.529 35.294 5ch 92 - 255 36.0 ( 1 , 2 ) 1dh 29 11.373 17.059 3dh 61 23.922 35.882 1eh 30 11.765 17.647 3eh 62 24.314 36.0 ( 1 , 2 ) 1fh 31 12.157 18.235 3fh 63 24.706 note 1: calculated r bw voltage is greater than 36v (highlighted in color), must be limited to 36v (v+ - v-). 2: this wiper code and greater will limit the i bw current to less than the maximum supported terminal current (i t ). MCP41HVX1 ds20005207a-page 40 ? 2013 microchip technology inc. table 5-5: max v bw at each wiper code (r w = r fs = r zs = 0 ? ) for v+ - v- = 36v, 50k ? devices. table 5-6: max v bw at each wiper code (r w = r fs = r zs = 0 ? ) for v+ - v- = 36v, 100k ? devices. code v bw(max) code v bw(max) code v bw(max) hex dec r s(min) r s(max) hex dec r s(min) r s(max) hex dec r s(min) r s(max) 00h 0 0.000 0.000 10h 16 16.314 24,471 20h 32 32.627 01h 1 1.020 1.529 11h 17 17.333 26.000 21h 33 33.647 02h 2 2.039 3.059 12h 18 18.353 27.529 22h 34 34.667 03h 3 3.059 4.588 13h 19 19.373 29.059 23h 35 35.686 04h 4 4.078 6.118 14h 20 20.392 30.588 24h - ffh 36 - 255 36.0 ( 1 , 2 ) 05h 5 5.098 7.647 15h 21 21.412 32.118 06h 6 6.118 9.176 16h 22 22.431 33.647 07h 7 7.137 10.706 17h 23 23.451 35.176 08h 8 8.157 12.235 18h 24 24.471 36.0 ( 1 , 2 ) 09h 9 9.176 13.765 19h 25 25.490 0ah 10 10.196 15.294 1ah 26 26.510 0bh 11 11.216 16.824 1bh 27 27.529 0ch 12 12.235 18.353 1ch 28 28.549 0dh 13 13.255 19.882 1dh 29 29.569 0eh 14 14.275 21.412 1eh 30 30.588 0fh 15 15.294 22.941 1fh 31 31.608 note 1: calculated r bw voltage is greater than 36v (highlighted in color), must be limited to 36v (v+ - v-). 2: this wiper code and greater will limit the i bw current to less than the maximum supported terminal current (i t ). code v bw(max) code v bw(max) hex dec r s(min) r s(max) hex dec r s(min) r s(max) 00h 0 0.000 0.000 10h 16 32.627 01h 1 2.039 3.059 11h 17 34.667 02h 2 4.078 6.118 12h - ffh 18 - 255 36.0 ( 1 , 2 ) 03h 3 6.118 9.176 04h 4 8.157 12.235 05h 5 10.196 15.294 06h 6 12.235 18.353 07h 7 14.275 21.412 08h 8 16.314 24.471 09h 9 18.353 27.529 0ah 10 20.392 30.588 0bh 11 22.431 33.647 0ch 12 24.471 36.0 ( 1 , 2 ) 0dh 13 26.510 0eh 14 28.549 0fh 15 30.588 note 1: calculated r bw voltage is greater than 36v (highlighted in color), must be limited to 36v (v+ - v-). 2: this wiper code and greater will limit the i bw current to less than the maximum supported terminal current (i t ). ? 2013 microchip technology inc. ds20005207a-page 41 MCP41HVX1 5.4 variable resistor (rheostat) a variable resistor is created using terminal w and either terminal a or terminal b. since the wiper-code value of 0 connects the wiper to the terminal b, the r bw resistance increases with increasing wiper code value. conversely, the r aw resistance will decrease with increasing wiper code value. figure 5-8 shows the con- nections from a potentiometer to create a rheostat con- figuration. figure 5-8: rheostat configuration. equation 5-4 shows the r bw and r aw calculations. the r bw calculation is for the resistance between the wiper and terminal b. the r aw calculation is for the resistance between the wiper and terminal a. equation 5-4: r bw and r aw calculation 5.5 analog circuitry power requirements this device has two power supplies. one is for the digital interface (vl and dgnd) and the other is for the high voltage analog circuitry (v+ and v-). the maximum delta voltage between v+ and v- is 36v. the digital power signals must be between v+ and v-. if the digital ground (dgnd) pin is at half the potential of v+ (relative to v-), then the terminal pins potentials can be (v+/2) relative to dgnd. figure 5-9 shows the relationship of the four power sig- nals. this shows that the v+ / v- signals do not need to be symmetric around the dgnd signal. to ensure that the wiper register has been properly loaded with the por/bor value, the v l voltage must be at the minimum specified operating voltage (refer- enced to dgnd). figure 5-9: analog circuitry voltage ranges. 5.6 resistor characteristics 5.6.1 v+ / v- low voltage operation the resistor network is specified from 20v to 36v. at voltages below 20v, the resistor network will function, but the operational characteristics may be outside the specified limits. please refer to section 2.0 ?typical performance curves? for additional information. 5.6.2 resistor tempco biasing the ends (terminal a and terminal b) near mid- supply ( (v+ - |v-| ) / 2 ) will give the worst switch resistance tempco. a b w resistor r aw r bw or r aw r bw where: r bw = r zs + ( n * r s ) simplified model (assumes r fs = r zs = 0 ? ) detailed model r bw = ( n * r s ) where: r s = r ab resolution n = wiper code n = wiper code 8-bit 7-bit r ab 255 r ab 127 r s = r s = r aw = ( ( fsv - n ) * r s ) fsv = the full scale vale (255 for 8-bit or 127 for 7-bit) fsv = the full scale vale (255 for 8-bit or 127 for 7-bit) r aw = r fs + ( ( fsv - n ) * r s ) dgnd voltages relative to dgnd v? ? v+ - v? voltage v+ v l +36v max +10v min this can be anywhere between v- and v+. MCP41HVX1 ds20005207a-page 42 ? 2013 microchip technology inc. 5.7 shutdown control shutdown is used to minimize the device?s current consumption. the MCP41HVX1 has two methods to achieve this: ? hardware shutdown pin (shdn) ? terminal control register (tcon) the hardware shutdown pin is backwards compatible with the mcp42x1 devices. 5.7.1 hardware shutdown pin (shdn ) the shdn pin is available on the potentiometer devices. when the shdn pin is forced active (v il ): ? the p0a terminal is disconnected ? the p0w terminal is connected to the p0b termi- nal (see figure 4-5 ) ? the serial interface is not disabled, and all serial interface activity is executed the hardware shutdown pin mode does not corrupt the values in the volatile wiper registers nor the tcon register. when the shutdown mode is exited (shdn pin is inactive (v ih )): ? the device returns to the wiper setting specified by the volatile wiper value ? the tcon register bits return to controlling the terminal connection state figure 5-10: hardware shutdown resistor network configuration. 5.7.2 terminal control register (tcon) the terminal control (tcon) register is a volatile register used to configure the connection of each resistor network terminal pin (a, b and w) to the resistor network. this register is shown in register 4- 1 . the r0hw bit forces the selected resistor network into the same state as the shdn pin. alternate low-power configurations may be achieved with the r0a, r0w and r0b bits. when the r0hw bit is ? 0 ?: ? the p0a terminal is disconnected ? the p0w terminal is simultaneously connect to the p0b terminal (see figure 5-11 ) the r0hw bit does not corrupt the values in the volatile wiper registers nor the tcon register. when the shutdown mode is exited (r0hw bit = 1 ): ? the device returns to the wiper setting specified by the volatile wiper value ? the tcon register bits return to controlling the terminal connection state figure 5-11: resistor network shutdown state (r0hw = 0 ). 5.7.3 interaction of shdn pin and tcon register figure 4-6 shows how the shdn pin signal and the r0hw bit signal interact to control the hardware shutdown of the resistor network. figure 5-12: r0hw bit and shdn pin interaction. a b w resistor network note: when the r0hw bit forces the resistor network into the hardware shdn state, the state of the tcon0 register?s r0a, r0w and r0b bits is overridden (ignored). when the state of the r0hw bit no longer forces the resistor network into the hardware shdn state, the tcon0 register?s r0a, r0w and r0b bits return to controlling the terminal connection state. in other words, the r0hw bit does not corrupt the state of the r0a, r0w and r0b bits. a b w resistor network shdn (from pin) r0hw (from tcon register) to pot 0 hardware shutdown control ? 2013 microchip technology inc. ds20005207a-page 43 MCP41HVX1 6.0 serial interface (spi) the MCP41HVX1 devices support the spi serial protocol. this spi operates in the slave mode (does not generate the serial clock). the device?s spi com- mand format operates on multiples of 8-bits. the spi interface uses up to four pins. these are: ?cs ? chip select ? sck ? serial clock ? sdi ? serial data in ? sdo ? serial data out a typical spi interface is shown in figure 6-1 . in the spi interface, the master?s output pin is connected to the slave?s input pin and the master?s input pin is connected to the slave?s output pin. the MCP41HVX1 spi?s module supports two (of the four) standard spi modes. these are mode 0,0 and 1,1. the spi mode is determined by the state of the sck pin (v ih or v il ) on the when the cs pin transitions from inactive (v ih ) to active (v il ). figure 6-1: typical spi interface block diagram. note: some host controller spi modules only operate with 16-bit transfers. for these host controllers, only the read and write commands may be used, or the continu- ous increment or decrement commands that are an even multiple of increment or decrement commands. sdi sdo MCP41HVX1 sdo sdi sck sck ( master out - slave in (mosi) ) ( master in - slave out (miso) ) host controller typical spi interface connections cs i/o wlat i/o shdn i/o MCP41HVX1 ds20005207a-page 44 ? 2013 microchip technology inc. 6.1 sdi, sdo, sck, and cs operation the operation of the four spi interface pins are discussed in this section. these pins are: ? serial data in (sdi) ? serial data out (sdo) ? serial clock (sck) ? the chip select signal (cs) the serial interface works on either 8-bit or 16-bit boundaries depending on the selected command. the chip select (cs ) pin frames the spi commands. 6.1.1 serial data in (sdi) the serial data in (sdi) signal is the data signal into the device. the value on this pin is latched on the rising edge of the sck signal. 6.1.2 serial data out (sdo) the serial data out (sdo) signal is the data signal out of the device. the value on this pin is driven on the falling edge of the sck signal. once the cs pin is forced to the active level (v il ), the sdo pin will be driven. the state of the sdo pin is determined by the serial bit?s position in the command, the command selected, and if there is a command error state (cmderr). 6.1.3 serial clock (sck) the serial clock (sck) signal is the clock signal of the spi module. the frequency of the sck pin determines the spi frequency of operation. the spi interface is specified to operate up to 10 mhz. the actual clock rate depends on the configuration of the system and the serial command used. table 6-1 shows the sck frequency. table 6-1: sck frequency 6.1.4 the chip select signal (cs ) the chip select (cs ) signal is used to select the device and frame a command sequence. to start a command, or sequence of commands, the cs signal must transition from the inactive state (v ih ) to an active state (v il ). after the cs signal has gone active, the sdo pin is driven and the clock bit counter is reset. if an error condition occurs for an spi command, then the command byte?s command error (cmderr) bit (on the sdo pin) will be driven low (v il ). to exit the error condition, the user must take the cs pin to the v ih level. when the cs pin returns to the inactive state (v ih ), the spi module resets (including the address pointer). while the cs pin is in the inactive state (v ih ), the serial interface is ignored. this allows the host controller to interface to other spi devices using the same sdi, sdo and sck signals. 6.1.5 low voltage support the serial interface is designed to also support 1.8v operation (at reduced specifications - frequency, thresholds, etc.). this allows the MCP41HVX1 device to interface to low-voltage host controllers. at 1.8v v l operation, the dgnd signal must be 0.9v or greater above the v- signal. if v l is 2.0v or greater, than the dgnd signal can be tied to the v- signal (see table 6-1 ). 6.1.6 split rail support the serial interface is designed to support split rail systems. in a split rail system, the microcontroller can operate at a lower voltage than the mcp41hxx1 device. this is achieved with the v ih specification. for v l ? 2.7v, the minimum v ih = 0.45 * v l . so if the microcontroller v oh at 1.8v is 0.8 * v dd , then v l can be a maximum of 3.2v (see equation 6-1 ). see section 8.1 for additional discussion on split rail support. equation 6-1: calculating max v l for microcontroller at 1.8v v l voltage command comment read write, increment, decrement 2.7v 10 mhz 10 mhz 1.8v 1 mhz 1 mhz dgnd = v- + 0.9v 2.0v 1 mhz 1 mhz dgnd = v- note: there is a required delay after the cs pin goes active to the 1st edge of the sck pin. if v oh = 0.8 * v dd = 0.8 * 1.8v = 1.44v then: v ih(min) = 1.44v with v ih = 0.45 * v l then: v l = 1.44v / 0.45 = 3.2v ? 2013 microchip technology inc. ds20005207a-page 45 MCP41HVX1 6.2 the spi modes the spi module supports two (of the four) standard spi modes. these are mode 0,0 and 1,1. the mode is determined by the state of the sdi pin on the rising edge of the first clock bit (of the 8-bit byte). 6.2.1 mode 0,0 in mode 0,0 : sck idle state = low (v il ), data is clocked in on the sdi pin on the rising edge of sck and clocked out on the sdo pin on the falling edge of sck. 6.2.2 mode 1,1 in mode 1,1 : sck idle state = high (v ih ), data is clocked in on the sdi pin on the rising edge of sck and clocked out on the sdo pin on the falling edge of sck. 6.3 spi waveforms figure 6-2 through figure 6-5 show the different spi command waveforms. figure 6-2 and figure 6-3 are read and write commands. figure 6-4 and figure 6-5 are increment and decrement commands. 6.4 daisy chaining this spi interface does not support daisy chaining. figure 6-2: 16-bit commands (write, read) ? spi waveform (mode 1,1). figure 6-3: 16-bit commands (write, read) ? spi waveform (mode 0,0). cs sck pic writes to sspbuf sdi input sample sdo bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ad3 ad2 ad1 ad0 c1 c0 x d8 d7 d6 d5 d4 d3 d2 d1 d0 v ih v il cmderr bit cs sck pic writes to sspbuf sdi input sample sdo bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ad3 ad2 ad1 ad0 c1 c0 x d8 d7 d6 d5 d4 d3 d2 d1 d0 v ih v il cmderr bit MCP41HVX1 ds20005207a-page 46 ? 2013 microchip technology inc. figure 6-4: 8-bit commands (increment, decrement) ? spi waveform with pic mcu (mode 1,1). figure 6-5: 8-bit commands (increment, decrement) ? spi waveform with pic mcu (mode 0,0). bit7 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cs sck pic writes to sspbuf sdi input sample sdo v ih v il ad3 ad2 ad1 ad0 c0 c1 x x ? 1 ? = valid command ? 0 ? = invalid command cmderr bit sck input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pic writes to sspbuf cs v ih v il ad3 ad2 ad1 ad0 c0 c1 x x ? 1 ? = valid command ? 0 ? = invalid command cmderr bit ? 2013 microchip technology inc. ds20005207a-page 47 MCP41HVX1 7.0 device commands the MCP41HVX1?s spi command format supports 16 memory address locations and four commands. these commands are shown in tab l e 7 - 1 . commands may be sent when the cs pin is driven to v il . the 8-bit commands ( increment wiper and dec- rement wiper commands) contain a command byte, see figure 7-1 , while 16-bit commands ( read data and write data commands) contain a command byte and a data byte. the command byte contains two data bits, see figure 7-1 . table 7-2 shows the supported commands for each memory location and the corresponding values on the sdi and sdo pins. table 7-1: commands 7.1 command format all commands have a command byte , which specifies the register address and the command. commands which require data (write and read commands), also have the data byte . 7.1.1 command byte the command byte has three fields, the address, the command, and two data bits, see figure 7-1 . currently only one of the data bits is defined (d8). this is for the write command. the device memory is accessed when the master sends a proper command byte to select the desired operation. the memory location to be accessed is con- tained in the command byte?s ad3:ad0 bits. the action desired is contained in the command byte?s c1:c0 bits, see tab l e 7 - 1 . c1:c0 determines if the desired memory location will be read, written, incremented (wiper set- ting +1) or decremented (wiper setting -1). the incre- ment and decrement commands are only valid on the volatile wiper registers. as the command byte is being loaded into the device (on the sdi pin), the device?s sdo pin is driving. the sdo pin will output high bits for the first six bits of that command. on the 7th bit, the sdo pin will output the cmderr bit state (see section 7.1.1.1 ?error condition? ). the 8th bit state depends on the command selected. figure 7-1: general spi command formats. c1:c0 bit states command name # of bits 11 read data 16-bits 00 write data 16-bits 01 increment wiper 8-bits 10 decrement wiper 8-bits a d 3 a d 2 a d 1 a d 0 c 1 c 0 d 9 d 8 memory command byte data address bits command bits a d 3 a d 2 a d 1 a d 0 c 1 c 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 memory 16-bit command data address bits command bits 0 0 = write data 0 1 = incr 1 0 = decr 1 1 = read data c c 1 0 command bits 8-bit command command byte data byte d9 d8 this bit is only used as the cmderr bit. this bit is not used. maintained for code compatibility with mcp41xx, mcp42xx, and mcp43xx devices. MCP41HVX1 ds20005207a-page 48 ? 2013 microchip technology inc. table 7-2: memory map and the supported commands address command data (10-bits) ( 1 ) spi string (binary) value function mosi (sdi pin) miso (sdo pin) ( 2 ) 00h volatile wiper 0 write data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn increment wiper ? 0000 0100 1111 1111 decrement wiper ? 0000 1000 1111 1111 01h - 03h ( 4 ) reserved ? ? ? ? 04h ( 3 ) volatile tcon register write data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn 05h - 0fh ( 4 ) reserved ? ? ? ? note 1: the data memory is 8-bits wide, so the two msbs (d9:d8) are ignored by the device. 2: all these address/command combinations are valid, so the cmderr bit is set. any other address/ command combination is a command error state and the cmderr bit will be clear. 3: increment or decrement commands are invalid for these addresses. 4: reserved addresses : any command is invalid for these addresses. ? 2013 microchip technology inc. ds20005207a-page 49 MCP41HVX1 7.1.1.1 error condition the cmderr bit indicates if the four address bits received (ad3:ad0) and the two command bits received (c1:c0) are a valid combination. the cmderr bit is high if the combination is valid and low if the combination is invalid (see tab le 7 -3 ). the command error bit will also be low if a write to a reserved address has been specified. spi commands that do not have a multiple of eight clocks are ignored. once an error condition has occurred, any following commands are ignored. all following sdo bits will be low until the cmderr condition is cleared by forcing the cs pin to the inactive state (v ih ). table 7-3: command error bit aborting a transmission all spi transmissions must have the correct number of sck pulses to be executed. the command is not executed until the complete number of clocks have been received. some commands also require the cs pin to be forced inactive (v ih ). if the cs pin is forced to the inactive state (v ih ), the serial interface is reset. partial commands are not executed. spi is more susceptible to noise than other bus protocols. the most likely case is that this noise corrupts the value of the data being clocked into the MCP41HVX1 or the sck pin is injected with extra clock pulses. this may cause data to be corrupted in the device, or a command error to occur, since the address and command bits were not a valid combination. the extra sck pulse will also cause the spi data (sdi) and clock (sck) to be out of sync. forcing the cs pin to the inactive state (v ih ) resets the serial interface. the spi interface will ignore activity on the sdi and sck pins until the cs pin transition to the active state is detected (v ih to v il ). 7.1.2 data byte only the read command and the write command use the data byte, see figure 7-1 . these commands concatenate the 8 bits of the data byte with the one data bit (d8) contained in the command byte to form 9- bits of data (d8:d0). the command byte format supports up to 9-bits of data, but the MCP41HVX1 only uses the lower 8-bits. that means that the full scale code of the 8-bit resistor network is ffh. when at full scale, the wiper connects to terminal a. the d8 bit is maintained for code compatibility with the mcp41xx, mcp42xx, and mcp43xx devices. the d9 bit is currently unused, and corresponds to the position on the sdo data of the cmderr bit. 7.1.3 continuous commands the device supports the ability to execute commands continuously while the cs pin is in the active state (v il ). any sequence of valid commands may be received. the following example is a valid sequence of events: 1. cs pin driven active (v il ). 2. read command. 3. increment command (wiper 0). 4. increment command (wiper 0). 5. decrement command (wiper 0). 6. write command. 7. read command. 8. cs pin driven inactive (v ih ). cmderr bit states description 1 ?valid? command/address combination 0 ?invalid? command/address combination note 1: when data is not being received by the MCP41HVX1, it is recommended that the cs pin be forced to the inactive level (v il ) 2: it is also recommended that long continuous command strings should be broken down into single commands or shorter continuous command strings. this reduces the probability of noise on the sck pin corrupting the desired spi commands. note 1: it is recommended that while the cs pin is active, only one type of command should be issued. when changing commands, it is recommended to take the cs pin inactive, then force it back to the active state. 2: it is also recommended that long command strings should be broken down into shorter command strings. this reduces the probability of noise on the sck pin corrupting the desired spi command string. MCP41HVX1 ds20005207a-page 50 ? 2013 microchip technology inc. 7.2 write data the write command is a 16-bit command. the format of the command is shown in figure 7-2 . a write command to a volatile memory location changes that location after a properly formatted write command (16-clock) has been received. 7.2.1 single write to volatile memory the write operation requires that the cs pin be in the active state (v il ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il ). the 16-bit write command (command byte and data byte) is then clocked (sck pin) in on the sdi pin. once all 16 bits have been received, the specified volatile address is updated. a write will not occur if the write command isn?t exactly 16 clocks pulses. figure 6-2 and figure 6-3 show possible waveforms for a single write. figure 7-2: write command ? sdi and sdo states. a d 3 a d 2 a d 1 a d 0 00 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1111111111111111valid address/command combination 111111 0 0 0 0 0 0 0 0 0 0 invalid address/command combination ( 1 ) command byte data byte sdi sdo note 1: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). ? 2013 microchip technology inc. ds20005207a-page 51 MCP41HVX1 7.2.2 continuous writes to volatile memory continuous writes are possible only when writing to the volatile memory registers (address 00h and 04h). figure 7-3 shows the sequence for three continuous writes. the writes do not need to be to the same volatile memory address. figure 7-3: continuous write sequence. a d 3 a d 2 a d 1 a d 0 00 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1111111*111111111 a d 3 a d 2 a d 1 a d 0 00 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1111111*111111111 a d 3 a d 2 a d 1 a d 0 00 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1111111*111111111 command byte data byte sdi sdo note 1: if a command error (cmderr) occurs at this bit location (*), then all following sdo bits will be driven low until the cs pin is driven inactive (v ih ). MCP41HVX1 ds20005207a-page 52 ? 2013 microchip technology inc. 7.3 read data the read command is a 16-bit command. the format of the command is shown in figure 7-4 . the first six bits of the read command determine the address and the command. the 7th clock will output the cmderr bit on the sdo pin. the 8th clock will be fixed at 1, and the remaining 8-clocks the device will transmit the eight data bits (d7:d0) of the specified address (ad3:ad0). figure 7-4 shows the sdi and sdo information for a read command. 7.3.1 single read the read operation requires that the cs pin be in the active state (v il ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il ). the 16-bit read command (command byte and data byte) is then clocked (sck pin) in on the sdi pin. the sdo pin starts driving data on the 7th bit (cmderr bit) and the addressed data comes out on the 8th through 16th clocks. figure 6-2 through figure 6-3 show possible waveforms for a single read. figure 7-4: read command ? sdi and sdo states. a d 3 a d 2 a d 1 a d 0 1 1xxxxxxxxxx 11111111d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 valid address/command combination 1111110000000000 attempted memory read of reserved memory location command byte data byte sdi sdo read data ? 2013 microchip technology inc. ds20005207a-page 53 MCP41HVX1 7.3.2 continuous reads continuous reads allow the device?s memory to be read quickly. continuous reads are possible to all memory locations. figure 7-5 shows the sequence for three continuous reads. the reads do not need to be to the same memory address. figure 7-5: continuous read sequence. a d 3 a d 2 a d 1 a d 0 1 1 x xxxxxxxxx 1111111* 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 3 a d 2 a d 1 a d 0 1 1 x xxxxxxxxx 1111111* 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 3 a d 2 a d 1 a d 0 1 1 x xxxxxxxxx 1111111* 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command byte data byte sdi sdo note 1: if a command error (cmderr) occurs at this bit location (*), then all following sdo bits will be driven low until the cs pin is driven inactive (v ih ). MCP41HVX1 ds20005207a-page 54 ? 2013 microchip technology inc. 7.4 increment wiper the increment command is an 8-bit command. the increment command can only be issued to specific volatile memory locations (the wiper register). the for- mat of the command is shown in figure 7-6 . an increment command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received. increment commands provide a quick and easy method to modify the value of the volatile wiper location by +1 with minimal overhead. figure 7-6: increment command ? sdi and sdo states. 7.4.1 single increment typically, the cs pin starts at the inactive state (v ih ), but may already be in the active state due to the completion of another command. figure 6-4 through figure 6-5 show possible waveforms for a single increment. the increment operation requires that the cs pin be in the active state (v il ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il ). the 8-bit increment command (command byte) is then clocked in on the sdi pin by the sck pins. the sdo pin drives the cmderr bit on the 7th clock. the wiper value will increment up to ffh on 8-bit devices and 7fh on 7-bit devices. after the wiper value has reached full scale (8-bit = ffh, 7-bit = 7fh), the wiper value will not be incremented further. see table 7-4 for additional information on the increment command versus the current volatile wiper value. the increment operations only require the increment command byte while the cs pin is active (v il ) for a single increment. after the wiper is incremented to the desired position, the cs pin should be forced to v ih to ensure that unexpected transitions on the sck pin do not cause the wiper setting to change. driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired increment occurs. table 7-4: increment operation vs. volatile wiper value note: table 7-2 shows the valid addresses for the increment wiper command. other addresses are invalid. a d 3 a d 2 a d 1 a d 0 01xx 1111111*1 note 1 , 2 111111 0 0 note 1 , 3 (incr command (n+1)) sdi sdo command byte note 1: only functions when writing the volatile wiper register (ad3:ad0 = 0h). 2: valid address/command combination. 3: invalid address/command combination all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). 4: if a command error (cmderr) occurs at this bit location (*), then all following sdo bits will be driven low until the cs pin is driven inactive (v ih ). current wiper setting wiper (w) properties increment command operates? 7-bit pot 8-bit pot 7fh ffh full scale (w = a) no 7eh 40h feh 80h w = n 3fh 7fh w = n (mid-scale) yes 3eh 01h 7eh 01h w = n 00h 00h zero scale (w = b) yes ? 2013 microchip technology inc. ds20005207a-page 55 MCP41HVX1 7.4.2 continuous increments continuous increments are possible only when writing to the volatile wiper registers (address 00h). figure 7-7 shows a continuous increment sequence. when executing a continuous increment command, the selected wiper will be altered from n to n+1 for each increment command received. the wiper value will increment up to ffh on 8-bit devices and 7fh on 7-bit devices. after the wiper value has reached full scale (8- bit = ffh, 7-bit = 7fh), the wiper value will not be incre- mented further. increment commands can be sent repeatedly without raising cs until a desired condition is met. when executing a continuous command string, the increment command can be followed by any other valid command. the wiper terminal will move after the command has been received (8th clock). after the wiper is incremented to the desired position, the cs pin should be forced to v ih to ensure that unexpected transitions (on the sck pin do not cause the wiper setting to change). driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired increment occurs. figure 7-7: continuous increment command ? sdi and sdo states. a d 3 a d 2 a d 1 a d 0 01xxa d 3 a d 2 a d 1 a d 0 01xxa d 3 a d 2 a d 1 a d 0 01xx 1111111*11111111*11111111*1 note 1 , 2 111111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note 3 , 4 111111 1 1111111 0 0 0 0 0 0 0 0 0 0 note 3 , 4 111111 1 1111111 1 1111111 0 0 note 3 , 4 (incr command (n+1)) (incr command (n+2)) (incr command (n+3)) sdi sdo command byte command byte command byte note 1: only functions when writing the volatile wiper register (ad3:ad0 = 0h). 2: valid address/command combination. 3: invalid address/command combination. 4: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). MCP41HVX1 ds20005207a-page 56 ? 2013 microchip technology inc. 7.5 decrement wiper the decrement command is an 8-bit command. the decrement command can only be issued to volatile wiper locations. the format of the command is shown in figure 7-8 . a decrement command to the volatile wiper location changes that location after a properly formatted command (8 clocks) have been received. decrement commands provide a quick and easy method to modify the value of the volatile wiper location by -1 with minimal overhead. figure 7-8: decrement command ? sdi and sdo states. 7.5.1 single decrement typically, the cs pin starts at the inactive state (v ih ), but may already be in the active state due to the completion of another command. figure 6-4 through figure 6-5 show possible waveforms for a single decrement. the decrement operation requires that the cs pin be in the active state (v il ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il ). then the 8- bit decrement command (command byte) is clocked in on the sdi pin by the sck pin. the sdo pin drives the cmderr bit on the 7th clock. the wiper value will decrement from the wiper?s full scale value (ffh on 8-bit devices and 7fh on 7-bit devices). if the wiper register has a zero scale value (00h), then the wiper value will not decrement. see table 7-5 for additional information on the decrement command vs. the current volatile wiper value. the decrement commands only require the decrement command byte, while the cs pin is active (v il or v ihh ) for a single decrement. after the wiper is decremented to the desired position, the cs pin should be forced to v ih to ensure that unexpected transitions on the sck pin do not cause the wiper setting to change. driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired decrement occurs. table 7-5: decrement operation vs. volatile wiper value note: table 7-2 shows the valid addresses for the decrement wiper command. other addresses are invalid. a d 3 a d 2 a d 1 a d 0 10xx 1111111*1 note 1 , 2 111111 0 0 note 1 , 3 (decr command (n+1)) sdi sdo command byte note 1: only functions when writing the volatile wiper registers (ad3:ad0 = 0h). 2: valid address/command combination. 3: invalid address/command combination, all following sdo bits will be low until the cmderr condition is cleared. (the cs pin is forced to the inactive state). 4: if a command error (cmderr) occurs at this bit location (*), then all following sdo bits will be driven low until the cs pin is driven inactive (v ih ). current wiper setting wiper (w) properties decrement command operates? 7-bit pot 8-bit pot 7fh ffh full scale (w = a) yes 7eh 40h feh 80h w = n 3fh 7fh w = n (mid-scale) yes 3eh 01h 7eh 01h w = n 00h 00h zero scale (w = b) no ? 2013 microchip technology inc. ds20005207a-page 57 MCP41HVX1 7.5.2 continuous decrements continuous decrements are possible only when writing to the volatile wiper register (address 00h). figure 7-9 shows a continuous decrement sequence. when executing continuous decrement commands, the selected wiper will be altered from n to n-1 for each decrement command received. the wiper value will decrement from the wiper?s full scale value (ffh on 8- bit devices and 7fh on 7-bit devices). if the wiper register has a zero scale value (00h), then the wiper value will not decrement. see table 7-5 for additional information on the decrement command vs. the current volatile wiper value. decrement commands can be sent repeatedly without raising cs until a desired condition is met. when executing a continuous command string, the decrement command can be followed by any other valid command. the wiper terminal will move after the command has been received (8th clock). after the wiper is decremented to the desired position, the cs pin should be forced to v ih to ensure that ?unexpected? transitions (on the sck pin do not cause the wiper setting to change). driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired decrement occurs. figure 7-9: continuous decrement command ? sdi and sdo states. a d 3 a d 2 a d 1 a d 0 10xxa d 3 a d 2 a d 1 a d 0 10xxa d 3 a d 2 a d 1 a d 0 10xx 1111111*11111111*11111111*1 note 1 , 2 111111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note 3 , 4 111111 1 1111111 0 0 0 0 0 0 0 0 0 0 note 3 , 4 111111 1 1111111 1 1111111 0 0 note 3 , 4 (decr command (n-1)) (decr command (n-1)) (decr command (n-1)) sdi sdo command byte command byte command byte note 1: only functions when writing the volatile wiper registers (ad3:ad0 = 0h). 2: valid address/command combination. 3: invalid address/command combination. 4: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). MCP41HVX1 ds20005207a-page 58 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds20005207a-page 59 MCP41HVX1 8.0 applications examples digital potentiometers have a multitude of practical uses in modern electronic circuits. the most popular uses include precision calibration of set point thresholds, sensor trimming, lcd bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. 8.1 split rail applications split rail applications are when one device operates from one voltage level (rail) and the second device operates from a second voltage level (rail). the typical scenario will be when the microcontroller is operating at a lower voltage level (for power savings, etc) and the MCP41HVX1 is operating at a higher voltage level to maximize operational performance. this configuration is shown in figure 8-1 . to ensure that communication properly occurs between the devices, care must be done to verify the compatibility of the v il , v ih , v ol , v oh levels of the interface signals between the devices. these interface signals are: ?cs ?sck ?sdi ?sdo ? shdn ?wlat when the microcontroller is at a lower voltage rail, the v oh of the microcontroller needs to be greater than the v ih of the MCP41HVX1, and the v il of the microcon- troller needs to be greater than the v ol of the MCP41HVX1. table 8-1 shows the calculated maximum MCP41HVX1 v l based on the microcontroller?s minimum v oh . figure 8-1: example split rail system. table 8-1: MCP41HVX1 v l voltage based on microcontroller v oh figure 8-2: example pic ? microcontroller v oh characterization graph (v dd = 1.8v). note: v oh specifications typically have a current load specified. this is due to the pin expected to drive externally circuitry. if the pin is unloaded (or lightly loaded), then the v oh of the pin could approach the device v dd (this is dependent on the implementa- tion of the output driver circuit). for v ol , unloaded (or lightly loaded) pins could approach the device v ss . for v oh and v ol characterization graphs from an example microcontroller, see the pic16f1934 data sheet (ds41364), fig- ure 31-15 and figure 31-16. pic ? mcu MCP41HVX1 max v l v dd (minimum) v oh (minimum) ( 1 ) formula (with load) calculated 1.8v 0.7 * v dd 1.26v 2.8v 0.8 * v dd 1.44v 3.2v 0.85 * v dd 1.53v 3.4v 0.9 * v dd 1.62v 3.6v v dd 1.8v 4.0v v dd - 0.7v 1.1v 2.44v 2.7v 0.7 * v dd 1.89v 4.2v 0.8 * v dd 2.16v 4.8v 0.9 * v dd 2.43v 5.4v v dd 2.7v 5.5v note 1: the v oh minimum voltage is determined by the load on the pin. if the load is small, a typical output?s voltage should approach the device?s v dd voltage. this is depen- dent on the device?s output driver design. 2: split rail voltages are dependent on v il , v ih , v ol , and v oh of the microcontroller and the MCP41HVX1 devices. voltage regulator 2.0v (1.8v min) 3.0v pic ? mcu MCP41HVX1 sdi cs sck wlat sdo cs sck i/o sdo sdi shdn i/o MCP41HVX1 ds20005207a-page 60 ? 2013 microchip technology inc. 8.2 using shutdown modes figure 8-3 shows a possible application circuit where the independent terminals could be used. disconnecting the wiper allows the transistor input to be taken to the bias voltage level (disconnecting a and or b may be desired to reduce system current). disconnecting terminal a modifies the transistor input by the r bw rheostat value to the common b. disconnecting terminal b modifies the transistor input by the r aw rheostat value to the common a. the common a and common b connections could be connected to v+ and v-. figure 8-3: example application circuit using terminal disconnects. 8.3 high-voltage dac a high-voltage dac can be implemented using the mcp41hvxx, with voltages as high as 36v. the circuit is shown in figure 8-4 . the equation to calculate the voltage output is shown in figure 8-1 . figure 8-4: high voltage dac. equation 8-1: dac output voltage calculation balance bias w b input input to base of transistor (or amplifier) a common b common a r 2 opa170 r 1 d 1 mcp41hvxx a b opa170 v out v+ v+ v+ + + - - v d high voltage dac n = 0 to 255 (decimal) v out (n) = x ( v d x ( 1 + ) ) r1 r2 n 255 7-bit 8-bit n = 0 to 127 (decimal) v out (n) = x ( v d x ( 1 + ) ) r1 r2 n 127 ? 2013 microchip technology inc. ds20005207a-page 61 MCP41HVX1 8.4 variable gain instrumentation amplifier a variable gain instrumentation amplifier can be implemented using the mcp41hvxx along with a high voltage dual analog switch and a high voltage instrumentation amplifier. figure 8-4 . the equation to calculate the voltage output is shown in figure 8-1 . figure 8-5: variable gain instrumentation amplifier for data acquisition system. equation 8-2: dac output voltage calculation 8.5 audio volume control a digital volume control can be implemented with the mcp41hvxx. figure 8-6 shows a simple audio volume control implementation. figure 8-7 shows a circuit-referenced voltage detect circuit. the output of this circuit could be used to control the wiper latch of the mcp41hvxx device in the audio volume control circuit to reduce zipper noise or to update the different channels at the same time. the op amp (u1) could be an mcp6001, while the gen- eral purpose comparators (u2 and u3) could be an mcp6541. u4 is a simple and gate. u1 establishes the signal zero reference. the upper limit of the comparator is set above its offset. the wlat pin is forced high whenever the voltage falls between 2.502v and 2.497v (a 0.005v window). the capacitor c1 ac couples the v in signal into the cir- cuit, before feeding into the windowed comparator (and mcp41hvxx terminal a pin). figure 8-6: audio volume control. figure 8-7: referenced voltage crossing detect. a ad8221 v out v+ b w mcp41hvxx da db adg1207 s1a s8a s1b s8b gain(n) = 1 + 49.4 k ? (n / 255) x r ab n = 0 to 255 (decimal) 7-bit 8-bit gain(n) = 1 + 49.4 k ? (n / 127) x r ab n = 0 to 127 (decimal) mcp41hvxx a b v out v+ v+ v in v- v- sdi sck wlat v l gnd + - r 1 r 5 wlat +5v +5v v in +5v r 2 100 k ? +5v r 3 r 4 100 k ? 200 k ? 10 k ? 90 k ? + - + - + - c 1 1f u1 u2 u3 u4 MCP41HVX1 ds20005207a-page 62 ? 2013 microchip technology inc. 8.6 programmable power supply the adp1611 is a step-up dc-to-dc switching con- verter. using the mcp41hvxx device allows the power supply to be programmable up to 20v. figure 8-7 shows a programmable power supply implementation. equation 8-3 shows the equation to calculate the output voltage of the programmable power supply. this output is derived from the r bw resistance of the mcp41hvxx device and the r 2 resistor. the adp1611 will adjust its output voltage to maintain 1.23v on the fb pin. when power is connected, l1 acts as a short, and v out is a diode drop below the +5v voltage. the v out voltage will ramp to the programmed value. figure 8-8: programmable power supply. equation 8-3: power supply output voltage calculation 8.7 programmable bidirectional current source a programmable bidirectional current source can be implemented with the mcp41hvxx. figure 8-9 shows an implementation where u1 and u2 work together to deliver the desired current (dependent on selected device) in both directions. the circuit is symmetrical (r 1a =r 1b , r 2a =r 2b , r 3a =r 3b ) in order to improve stability. if the resistors are matched, the load current (i l ) calculation is shown below: equation 8-4: load current (i l ) figure 8-9: programmable bidirectional current source. mcp41hvxx a b v out r 1 d 1 adp1611 +5v w v+ c 1 0.1 f 220 k ? 8.5 k ? in sw comp rt fb ss c 5 10 f c 4 150 pf c 3 22 nf c 2 10 f r 2 (100 k ? ) l1 4.7 f n = 0 to 255 (decimal) v out (n) = 1.23v x ( 1 + ( ) ) r 2 n * r ab 255 7-bit 8-bit n = 0 to 127 (decimal) v out (n) = 1.23v x ( 1 + ( ) ) r 2 n * r ab 127 i l = x v w (r 2a + r 3a ) r 1a * r 3a r 1a +15v +15v 150 k ? r 3a r 4 50 k ? 500 ? + - - + c 1 10 pf u2 u1 mcp41hvxx a b w v+ v- -15v -15v v l c 2 10 pf r 2a 14.95 k ? r 1b 150 k ? r 2b 15 k ? i l r 3b 50 k ? ? 2013 microchip technology inc. ds20005207a-page 63 MCP41HVX1 8.8 lcd contrast control the mcp41hvxx can be used for lcd contrast control. figure 8-10 shows a simple programmable lcd contrast control implementation. some lcd panels support a fixed power supply of up to 28v. the high voltage digital potentiometer's wiper can support contrast adjustments through the entire voltage range. figure 8-10: programmable contrast control. 8.9 serial interface communication times table 8-2 shows the time for each spi serial interface command as well as the effective data update rate that can be supported by the digital interface (based on the two spi serial interface frequencies). so, the serial interface performance, along with the wiper response time, would be used to determine your application?s volatile wiper register update rate. table 8-2: serial interface times / frequencies mcp41hvxx a b d 1 lcd panel w c 1 10 f v out (lcd bias) fixed +16v to +26v contrast adj. ucontroller sdo sck cs (up to +28v) command # of serial interface bits example command time (s) effective data update frequency (khz) ( 2 ) # bytes transferred # of serial interface bits 1mhz 10mhz 1mhz 10mhz write single byte 16 1 16 16 1.6 62,500 625,000 write continuous bytes n * 16 5 80 80 8 12,500 125,000 read byte 16 1 16 16 1.6 62,500 625,000 read continuous bytes n * 16 5 80 80 8 12,500 125,000 increment wiper 8 1 8 8 0.8 125,000 1,250,000 continuous increments n * 8 5 40 40 4 25,000 250,000 decrement wiper 8 1 8 8 0.8 125,000 1,250,000 continuous decrements n * 8 5 40 40 4 25,000 250,000 note 1: includes the start or stop bits. 2: this is the command frequency multiplied by the number of bytes transferred. MCP41HVX1 ds20005207a-page 64 ? 2013 microchip technology inc. 8.10 design considerations in the design of a system with the MCP41HVX1 devices, the following considerations should be taken into account: ? power supply considerations ? layout considerations 8.10.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply?s traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-11 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v l ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v+ and v- should reside on the analog plane. figure 8-11: typical microcontroller connections. 8.10.2 layout considerations in the design of a system with the MCP41HVX1 devices, the following layout considerations should be taken into account: ? noise ? pcb area requirements ? power dissipation 8.10.2.1 noise inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP41HVX1?s performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. particularly harsh environments may require shielding of critical signals. if low noise is desired, breadboards and wire-wrapped boards are not recommended. 8.10.2.2 pcb area requirements in some applications, pcb area is a criteria for device selection. table 8-3 shows the package dimensions and area for the different package options. the table also shows the relative area factor compared to the smallest area. for space critical applications, the qfn package would be the suggested package. table 8-3: package footprint ( 1 ) v l v dd dgnd v ss mcp41hvxx 0.1 f pic ? microcontroller 0.1 f sdi cs w b a sdo sck v+ 0.1 f v- v- package package footprint pins type code dimensions (mm) area (mm 2 ) relative area xy 14 tssop st 5.10 6.40 32.64 1.31 20 qfn mq 5.00 5.00 25.00 1 note 1: does not include recommended land pattern dimensions. ? 2013 microchip technology inc. ds20005207a-page 65 MCP41HVX1 8.10.3 resistor tempco characterization curves of the resistor temperature coefficient (tempco) are shown in the device character- ization graphs. these curves show that the resistor network is designed to correct for the change in resistance as temperature increases. this technique reduces the end-to-end change in r ab resistance. 8.10.3.1 power dissipation the power dissipation of the high-voltage digital poten- tiometer will most likely be determined by the power dissipation through the resistor networks. table 8-4 shows the power dissipation through the resistor ladder (r ab ) when terminal a = +18v and terminal b = -18v. this is not the worst case power dissipation based on the 25 ma terminal current specification. ta b l e 8 - 4 show the worst case current (per resistor network), which is independent of the r ab value). table 8-4: r ab power dissipation table 8-5: r bw power dissipation r ab resistance ( ? )| v a | + |v b | = (v) power (mw) ( 1 ) typical min max 5,000 4,000 6,000 36 324 10,000 8,000 12,000 36 162 50,000 40,000 60,000 36 32.4 100,000 80,000 120,000 36 16.2 note 1: power = v * i = v 2 / r ab(min) . r ab ( ? ) (typical) | v w | + |v b | = (v) ibw ( 2 ) (ma) power (mw) ( 1 ) 5,000 36 25 900 10,000 36 12.5 450 50,000 36 6.5 234 100,000 36 6.5 234 note 1: power = v * i. 2: see electrical specifications (max i w ). MCP41HVX1 ds20005207a-page 66 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds20005207a-page 67 MCP41HVX1 9.0 device options 9.1 standard options 9.1.1 por/bor wiper setting the default wiper setting (mid-scale) is indicated by the customer in three digit suffix: -202, -502, -103 and -503. table 9-1 indicates the device?s default settings. table 9-1: default por/bor wiper setting selection 9.2 custom options custom options can be made available. 9.2.1 custom wiper value on por/ bor event customers can specify a custom wiper setting via the nscar process. typical r ab value package code default por wiper setting device resolution wiper code 5.0 k ? -502 mid-scale 8-bit 7fh 7-bit 3fh 10.0 k ? -103 mid-scale 8-bit 7fh 7-bit 3fh 50.0 k ? -503 mid-scale 8-bit 7fh 7-bit 3fh 100.0 k ? -104 mid-scale 8-bit 7fh 7-bit 3fh note 1: non-recurring engineering (nre) charges and minimum ordering require- ments for custom orders. please contact microchip sales for additional information. 2: a custom device will be assigned custom device marking. MCP41HVX1 ds20005207a-page 68 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds20005207a-page 69 MCP41HVX1 10.0 development support 10.1 development tools several development tools are available to assist in your design and evaluation of the MCP41HVX1 devices. the currently available tools are shown in table 10-1 . figure 10-1 shows how the tssop20ev bond-out pcb can be populated to easily evaluate the MCP41HVX1 devices. evaluation can use the pickit? serial analyzer to control the position of the volatile wiper and state of the tcon register. figure 10-2 shows how the soic14ev bond-out pcb can be populated to evaluate the MCP41HVX1 devices. the use of the pickit serial analyzer would require blue wire since the header h1 is not compatibly connected. these boards may be purchased directly from the microchip web site at www.microchip.com . 10.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. ta b l e 1 0 - 2 shows some of these documents. table 10-1: development tools table 10-2: technical documentation board name part # comment 20-pin tssop and ssop evaluation board tssop20ev can easily interface to pickit serial analyzer (order #: dv164122) 14-pin soic/tssop/dip evaluation board soic14ev application note number title literature # tb3073 implementing a 10-bit digital potentiometer with an 8-bit digital potentiometer ds93073 an1316 using digital potentiometers for programmable amplifier gain ds01316 an1080 understanding digital potentiometers resistor variations ds01080 an737 using digital potentiometers to design low-pass adjustable filters ds00737 an692 using a digital potentiometer to optimize a precision single supply photo detect ds00692 an691 optimizing the digital potentiometer in precision circuits ds00691 an219 comparing digital potentiometers to mechanical potentiometers ds00219 ? digital potentiometer design guide ds22017 ? signal chain design guide ds21825 ? analog solutions for automotive applications design guide ds01005 MCP41HVX1 ds20005207a-page 70 ? 2013 microchip technology inc. figure 10-1: digital potentiometer evaluation board circuit using tssop20ev. 0 ? 0 ? 0 ? 0 ? 41hvx1 four blue wire jumpers to connect pickit ? serial interface (spi) to device pins 1x6 male header, with 90 right angle MCP41HVX1-xxxe/st installed in u3 (bottom 14 pins of tssop-20 footprint) connected to digital ground connected to digital power (v l ) plane through-hole test point (orange) wiper 0 vl sck cs sdi sdo v+ p0a p0w p0b v- (dgnd) plane wlat shdn dgnd nc 0 ? 1.0 f p0a pin shorted (jumpered) to v+ pin p0b pin shorted (jumpered) to v- pin ? 2013 microchip technology inc. ds20005207a-page 71 MCP41HVX1 figure 10-2: digital potentiometer evaluation board circuit using soic14ev. MCP41HVX1 1.0 f vl sck cs sdi sdo wlat shdn v+ p0a p0w p0b v- dgnd nc 0 ? 0 ? 0 ? 0 ? MCP41HVX1 ds20005207a-page 72 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds20005207a-page 73 MCP41HVX1 11.0 packaging information 11.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code rohs compliant jedec designator for matte tin (sn) * this package is rohs compliant. the rohs compliant jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 20-lead qfn (5x5x0.9 mm) example pin 1 pin 1 3 e 14-lead tssop (4.4 mm) example yyww nnn xxxxxxxx part number code part number code mcp41hv51-502e/st 41h51502 mcp41hv31-502e/st 41h31502 mcp41hv51-103e/st 41h51103 mcp41hv31-103e/st 41h31103 mcp41hv51-503e/st 41h51503 mcp41hv31-503e/st 41h31503 mcp41hv51-104e/st 41h51104 mcp41hv31-104e/st 41h31104 41h51502 e320 256 part number code part number code mcp41hv51-502e/mq 502e/mq mcp41hv31-502e/mq 502e/mq mcp41hv51-103e/mq 103e/mq mcp41hv31-103e/mq 103e/mq mcp41hv51-503e/mq 503e/mq mcp41hv31-503e/mq 503e/mq mcp41hv51-104e/mq 104e/mq mcp41hv31-104e/mq 104e/mq 41hv31 502e/mq 1320256 MCP41HVX1 ds20005207a-page 74 ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2013 microchip technology inc. ds20005207a-page 75 MCP41HVX1 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging MCP41HVX1 ds20005207a-page 76 ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2013 microchip technology inc. ds20005207a-page 77 MCP41HVX1 d exposed pad e e2 2 1 n top view note 1 n l k b e d2 2 1 a a1 a3 bottom view MCP41HVX1 ds20005207a-page 78 ? 2013 microchip technology inc. ? 2013 microchip technology inc. ds20005207a-page 79 MCP41HVX1 appendix a: revision history revision a (may 2013) ? original release of this document. appendix b: terminology this appendix discusses the terminology used in this document as well as describes how a parameter is measured. b.1 potentiometer (voltage divider) the potentiometer configuration is when all three terminals of the device are tied to different nodes in the circuit. this allows the potentiometer to output a voltage proportional to the input voltage. this configuration is sometimes called voltage divider mode. the potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in figure b-1 . reversing the polarity of the a and b terminals will not affect operation. figure b-1: potentiometer configuration. the temperature coefficient of the r ab resistors is minimal by design. in this configuration, the resistors all change uniformly, so minimal variation should be seen. b.2 rheostat (variable resistor) the rheostat configuration is when two of the three dig- ital potentiometer?s terminals are used as a resistive element in the circuit. with terminal w (wiper) and either terminal a or terminal b, a variable resistor is created. the resistance will depend on the tap setting of the wiper (and the wiper?s resistance). the resistance is controlled by changing the wiper setting. figure b-2 shows the two possible resistors that can be used. reversing the polarity of the a and b terminals will not affect operation. figure b-2: rheostat configuration. a b w v 1 v 3 v 2 a b w resistor r aw r bw or MCP41HVX1 ds20005207a-page 80 ? 2013 microchip technology inc. b.3 resolution the resolution is the number of wiper output states that divide the full-scale range. for the 8-bit digital potentiometer, the resolution is 2 8 , meaning the digital potentiometer wiper code ranges from 0 to 255. b.4 step resistance (r s ) the resistance step size (r s ) equates to one lsb of the resistor ladder. equation b-1 shows the calculation for the step resistance (r s ). equation b-1: r s calculation b.5 wiper resistance wiper resistance is the series resistance of the analog switch that connects the selected resistor ladder node to the wiper terminal common signal (see figure 5-1 ). a value in the volatile wiper register selects which analog switch to close, connecting the w terminal to the selected node of the resistor ladder. the resistance is dependent on the voltages on the analog switch source, gate, and drain nodes, as well as the device?s wiper code, temperature, and the current through the switch. as the device voltage decreases, the wiper resistance increases. the wiper resistance is measured by forcing a current through the w and b terminals (i wb ) and measuring the voltage on the w and a terminals (v w and v a ). equation b-2 shows how to calculate this resistance. equation b-2: r w calculation the wiper resistance in potentiometer-generated voltage divider applications is not a significant source of error (it does not effect the output voltage seen on the w pin). the wiper resistance in rheostat applications can create significant nonlinearity as the wiper is moved toward zero scale (00h). the lower the nominal resistance, the greater the possible error. b.6 r zs resistance the analog switch between the resistor ladder and the terminal b pin introduces a resistance, which we call the zero-scale resistance (r zs ). equation b-3 shows how to calculate this resistance. equation b-3: r zs calculation b.7 r fs resistance the analog switch between the resistor ladder and the terminal a pin introduces a resistance, which we call the full-scale resistance (r fs ). equation b-4 shows how to calculate this resistance. equation b-4: r fs calculation b.8 least significant bit (lsb) this is the difference between two successive codes (either in resistance or voltage). for a given output range it is divided by the resolution of the device ( equation b-5 ). 2 n - 1 = 255 (mcp41hv51/61) = 127 (mcp41hv31/41) r s(ideal) = or ideal r ab 2 n -1 r s(measured) = measured (v w(@fs) - v w(@zs) ) / i ab 2 n - 1 where: v a = voltage on terminal a pin v b = voltage on terminal b pin i ab = measured current through a and b pins v w(@fs) = measured voltage on w pin at full-scale code (ffh or 7fh) v w(@zs) = measured voltage on w pin at zero-scale code (00h) (v a - v b ) / i ab 2 n -1 r w(measured) = (v w - v a ) i wb where: v a = voltage on terminal a pin v w = voltage on terminal w pin i wb = measured current through w and b pins r zs(measured) = (v w(@zs) - v b ) i ab where: v w(@zs) = voltage on terminal w pin v b = voltage on terminal b pin i wb = measured current through a and b pins at zero-scale wiper code r fs(measured) = (v a - v w(@fs) ) i ab where: v a = voltage on terminal a pin v w(@fs) = voltage on terminal w pin i wb = measured current through a and b pins at full-scale wiper code ? 2013 microchip technology inc. ds20005207a-page 81 MCP41HVX1 equation b-5: lsb calculation b.9 monotonic operation monotonic operation means that the device?s output (resistance (r bw ) or voltage (v w )) increases with every one code step (lsb) increment of the wiper register. figure b-3: theoretical v w output vs code (monotonic operation). figure b-4: theoretical r bw output vs code (monotonic operation). 2 n - 1 = 255 (mcp41hv51/61) = 127 (mcp41hv31/41) in resistance in voltage lsb(ideal) = ideal r ab 2 n -1 v a - v b 2 n - 1 lsb(measured) = v w(@fs) - v w(@zs) 2 n - 1 measured (v w(@fs) - v w(@zs) ) / i ab 2 n - 1 where: v a = voltage on terminal a pin v b = voltage on terminal b pin v ab = measured voltage between a and b pins i ab = measured current through a and b pins v w(@fs) = measured voltage on w pin at full-scale code (ffh or 7fh) v w(@zs) = measured voltage on w pin at zero-scale code (00h) 0x40 0x3f 0x3e 0x03 0x02 0x01 0x00 wiper code voltage (v w ~= v out ) v w (@ tap) v s0 v s1 v s3 v s63 v s64 v w = v sn + v zs(@ tap 0) n = 0 n = ? 0x3f 0x3e 0x3d 0x03 0x02 0x01 0x00 digital input code resistance (r bw ) r w (@ tap) r s0 r s1 r s3 r s62 r s63 r bw = r sn + r w(@ tap n) n = 0 n = ? MCP41HVX1 ds20005207a-page 82 ? 2013 microchip technology inc. b.10 full-scale error (e fs ) the full-scale error (see figure b-5 ) is the error of the v w pin relative to the expected v w voltage (theoretical) for the maximum device wiper register code (code ffh for 8-bit and code 7fh for 7-bit), see equation b-6 . the error is dependent on the resistive load on the v out pin (and where that load is tied to, such as v ss or v dd ). for loads (to v ss ) greater than specified, the full scale error will be greater. the error in bits is determined by the theoretical voltage step size to give an error in lsb. equation b-6: full-scale error figure b-5: full-scale error example. b.11 zero-scale error (e zs ) the zero-scale error (see figure b-6 ) is the difference between the ideal and measured v out voltage with the wiper register code equal to 00h ( equation b-7 ). the error is dependent on the resistive load on the v out pin (and where that load is tied to, such as v ss or v dd ). for loads (to v dd ) greater than specified, the zero scale error will be greater. the error in bits is determined by the theoretical voltage step size to give an error in lsb. equation b-7: zero scale error figure b-6: zero-scale error example. note: analog switch leakage increases with tem- perature. this leakage increase substan- tially at higher temperatures (> ~100c). as analog switch leakage increases, the full-scale output value decreases, which increases the full-scale error. e fs = v w(@fs) - v a v lsb(ideal) where: e fs is expressed in lsb v w@fs) is the v w voltage when the wiper register code is at full-scale. v ideal(@fs) is the ideal output voltage when the wiper register code is at full-scale. v lsb(ideal) is the theoretical voltage step size. v w ideal transfer actual wiper code 0 full-scale error (e fs ) function full-scale v a transfer function v b v fs v zs note: analog switch leakage increases with tem- perature. this leakage increase substan- tially at higher temperatures (> ~100c). as analog switch leakage increases the zero-scale output value decreases, which decreases the zero-scale error. e zs = v w@zs) v lsb(ideal) where: e fs is expressed in lsb v w@zs) is the v w voltage when the wiper register code is at zero-scale. v lsb(ideal) is the theoretical voltage step size. v w ideal transfer actual wiper code 0 function full-scale v a transfer function v b v fs v zs zero-scale error (e zs ) ? 2013 microchip technology inc. ds20005207a-page 83 MCP41HVX1 b.12 integral non-linearity (p-inl) potentiometer configuration the potentiometer integral nonlinearity (p-inl) error is the maximum deviation of an actual v w transfer function from an ideal transfer function (straight line). in the MCP41HVX1, p-inl is calculated using the zero-scale and full-scale wiper code end points. p- inl is expressed in lsb. p-inl is also called relative accuracy. equation b-8 shows how to calculate the p- inl error in lsb and figure b-7 shows an example of p-inl accuracy. positive p-inl means higher v w voltage than ideal. negative p-inl means lower v w voltage than ideal. equation b-8: p-inl error figure b-7: p-inl accuracy. b.13 differential nonlinearity (p-dnl) potentiometer configuration the potentiometer differential nonlinearity (p-dnl) error (see figure b-8 ) is the measure of v w step size between codes. the ideal step size between codes is 1 lsb. a p-dnl error of zero would imply that every code is exactly 1 lsb wide. if the p-dnl error is less than 1 lsb, the digital potentiometer guarantees monotonic output and no missing codes. the p-dnl error between any two adjacent codes is calculated in equation b-9 . p-dnl error is the measure of variations in code widths from the ideal code width. equation b-9: p-dnl error figure b-8: p-dnl accuracy. note: analog switch leakage increases with tem- perature. this leakage increase substan- tially at higher temperatures (> ~100c). as analog switch leakage increases, the wiper output voltage (v w ) decreases, which effects the inl error. where: inl is expressed in lsb. code = wiper register value v w(@code) = the measured v w output voltage with a given wiper register code v lsb = for ideal: v ab / resolution for measured: (v w(@fs) - v w(@zs) ) / 255 e inl = ( v w(@code) - ( v lsb(measured) * code )) v lsb(measured) 111 110 101 100 011 010 001 000 wiper code actual transfer function inl < 0 ideal transfer function inl < 0 v w output voltage note: analog switch leakage increases with tem- perature. this leakage increase substan- tially at higher temperatures (> ~100c). as analog switch leakage increases, the wiper output voltage (v w ) decreases, which effects the dnl error. where: dnl is expressed in lsb. v w(code = n) = the measured v w output voltage with a given wiper register code. v lsb = for ideal: v ab / resolution for measured: (v w(@fs) - v w(@zs) ) / # of r s e dnl = ( v w(code = n+1) - v w(code = n) ) - v lsb(measured) ) v lsb(measured) 111 110 101 100 011 010 001 000 wiper code actual transfer function ideal transfer function narrow code < 1 lsb wide code, > 1 lsb v w output voltage MCP41HVX1 ds20005207a-page 84 ? 2013 microchip technology inc. b.14 integral non-linearity (r-inl) rheostat configuration the rheostat integral nonlinearity (r-inl) error is the maximum deviation of an actual r bw transfer function from an ideal transfer function (straight line). in the MCP41HVX1, inl is calculated using the zero- scale and full-scale wiper code end points. r-inl is expressed in lsb. r-inl is also called relative accuracy. equation b-10 shows how to calculate the r- inl error in lsb and figure b-9 shows an example of r-inl accuracy. positive r-inl means higher v out voltage than ideal. negative r-inl means lower v out voltage than ideal. equation b-10: r-inl error figure b-9: r-inl accuracy. b.15 differential nonlinearity (r-dnl) rheostat configuration the rheostat differential nonlinearity (r-dnl) error (see figure b-10 ) is the measure of r bw step size between codes in actual transfer function. the ideal step size between codes is 1 lsb. a r-dnl error of zero would imply that every code is exactly 1 lsb wide. if the r-dnl error is less than 1 lsb, the r bw resis- tance guarantees monotonic output and no missing codes. the r-dnl error between any two adjacent codes is calculated in equation b-11 . r-dnl error is the measure of variations in code widths from the ideal code width. a r-dnl error of zero would imply that every code is exactly 1 lsb wide. equation b-11: r-dnl error figure b-10: r-dnl accuracy. where: inl is expressed in lsb. r bw(code = n) = the measured r bw resistance with a given wiper register code r lsb = for ideal: r ab / resolution for measured: r bw(@fs) / # of r s e inl = ( r bw(@code) - r bw(ideal) ) r lsb(ideal) 111 110 101 100 011 010 001 000 wiper code actual transfer function inl < 0 ideal transfer function inl < 0 r bw resistance where: dnl is expressed in lsb. r bw(code = n) = the measured r bw resistance with a given wiper register code r lsb = for ideal: r ab / resolution for measured: r bw(@fs) / # of r s e dnl = ( v out(code = n+1) - v out(code = n) ) - v lsb(measured) ) v lsb(measured) 111 110 101 100 011 010 001 000 wiper code actual transfer function ideal transfer function narrow code < 1 lsb wide code, > 1 lsb r bw resistance ? 2013 microchip technology inc. ds20005207a-page 85 MCP41HVX1 b.16 total unadjusted error (e t ) the total unadjusted error (e t ) is the difference between the ideal and measured v w voltage. typically, calibration of the output voltage is implemented to improve system performance. the error in bits is determined by the theoretical voltage step size to give an error in lsb. equation b-12 shows the total unadjusted error calculation. equation b-12: total unadjusted error calculation b.17 settling time the settling time is the time delay required for the v w voltage to settle into its new output value. this time is measured from the start of code transition, to when the v w voltage is within the specified accuracy. it is related to the rc characteristics of the resistor ladder and wiper switches. in the MCP41HVX1, the settling time is a measure of the time delay until the v w voltage reaches within 0.5 lsb of its final value, when the volatile wiper register changes from zero scale to full scale (or full scale to zero scale). b.18 major-code transition glitch major-code transition glitch is the impulse energy injected into the wiper pin when the code in the wiper register changes state. it is normally specified as the area of the glitch in nv-sec, and is measured when the digital code is changed by 1 lsb at the major carry tran- sition (example: 01111111 to 10000000 , or 10000000 to 01111111 ). b.19 digital feedthrough the digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. the area of the glitch is expressed in nv-sec, and is measured with a full-scale change (example: all 0 s to all 1 s and vice versa) on the digital input pins. the digital feedthrough is measured when the digital potentiometer is not being written to the out- put register. b.20 power-supply sensitivity (pss) pss indicates how the output (v w or r bw ) of the digital potentiometer is affected by changes in the supply volt- age. pss is the ratio of the change in v w to a change in v dd for mid-scale output of the digital potentiometer. the v w is measured while the v dd is varied from 5.5v to 2.7v as a step, and expressed in % / %, which is the % change of the v w output voltage with respect to the % change of the v dd voltage. equation b-13: pss calculation b.21 power-supply rejection ratio (psrr) psrr indicates how the output of the digital potentiom- eter is affected by changes in the supply voltage. psrr is the ratio of the change in v w to a change in v dd for full-scale output of the digital potentiometer. the v w is measured while the v dd is varied +/- 10% (v a and v b voltages held constant), and expressed in db or v/v. note: analog switch leakage increases with tem- perature. this leakage increase substan- tially at higher temperatures (> ~100c). as analog switch leakage increases, the wiper output voltage (v w ) decreases, which effects the total unadjusted error. where: e t is expressed in lsb. v w_actual(@code) = the measured w pin output voltage at the specified code v w_ideal(@code) = the calculated w pin output voltage at the specified code ( code * v lsb(ideal) ) v lsb(ideal) = v ab / # r s 8-bit = v ab / 255 7-bit = v ab / 127 e t = ( v w_actual(@code) - v w_ideal(@code) ) v lsb(ideal) where: pss is expressed in % / %. v w(@5.5v) = the measured v w output voltage with v dd = 5.5v v w(@2.7v) = the measured v w output voltage with v dd = 2.7v pss = ( v w(@5.5v) - v w(@2.7v) ) / v w(@5.5v) ) (5.5v - 2.7v) / 5.5v MCP41HVX1 ds20005207a-page 86 ? 2013 microchip technology inc. b.22 ratiometric temperature coefficient the ratiometric temperature coefficient quantifies the error in the ratio r aw /r wb due to temperature drift. this is typically the critical error when using a digital potentiometer in a voltage divider configuration. b.23 absolute temperature coefficient the absolute temperature coefficient quantifies the error in the end-to-end resistance (nominal resistance r ab ) due to temperature drift. this is typically the critical error when using the device in an adjustable resistor configuration. characterization curves of the resistor temperature coefficient (tempco) are shown in section 2.0 ?typi- cal performance curves? . b.24 -3db bandwidth this is the frequency of the signal at the a terminal, that causes the voltage at the w pin to fall -3 db value from that value of a static value on the a terminal. the output decreases due to the rc characteristics of the resistor network. b.25 resistor noise density (e n_wb ) this is the random noise generated by the device?s internal resistances. it is specified as a spectral density (voltage per square root hertz). ? 2013 microchip technology inc. ds20005207a-page 87 MCP41HVX1 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp41hv31: single potentiometer (7-bit) with spi interface mcp41hv31t: single potentiometer (7-bit) with spi interface (tape and reel) mcp41hv51: single potentiometer (8-bit) with spi interface mcp41hv51t: single potentiometer (8-bit) with spi interface (tape and reel) resistance version: 502 = 5 k ? 103 = 10 k ? 503 = 50 k ? 104 = 100 k ? temperature range: e = -40c to +125c package: st = plastic tssop-14, 14-lead mq = plastic qfn-20 (5x5), 20-lead part no. x /xx package temperature range device examples: a) mcp41hv51t-502e/st 5k ? , 8-bit, 14-ld tssop. b) mcp41hv51t-103e/st 10 k ? , 8-bit, 14-ld tssop. c) mcp41hv31t-503e/st 50 k ? , 7-bit, 14-ld tssop. d) mcp41hv31t-104e/mq 100 k ? , 7-bit, 20-ld qfn (5x5). a) mcp41hv51t-502e/mq 5k ? , 8-bit, 20-ld qfn (5x5). b) mcp41hv51t-103e/mq 10 k ? , 8-bit, 20-ld qfn (5x5). c) mcp41hv31t-503e/mq 50 k ? , 7-bit, 20-ld qfn (5x5). d) mcp41hv31t-104e/mq 100 k ? , 7-bit, 20-ld qfn (5x5). xxx resistance version MCP41HVX1 ds20005207a-page 88 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds20005207a-page 89 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620772270 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == ds20005207a-page 90 ? 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